04-20-2021, 07:37 PM
Has anyone gotten the DDR3 module to work with the alchrity AU+ board? I followed the tutorial at
https://alchitry.com/blogs/tutorials/usi...lchitry-au
and also just ran a pure verilog version on Vivado, neither one of which appears to work. Lot's of other stuff is working on this board, but I've had no luck with the DDR3.
I have the xilinx DDR3 module instantiated, along with a MMCM clock synthesis generating 100Mhz input, 100Mhz to sys_clk_i and 200Mhz to clk_ref_i. Vivado synthesizes without error, but routing DRC complains about this:
[DRC PDRC-34] MMCM_adv_ClkFrequency_div_no_dclk: The computed value 200.000 MHz (CLKIN1_PERIOD, net pll_clk3) for the VCO operating frequency of the MMCME2_ADV site MMCME2_ADV_X0Y2 (cell i_mig_7series_0/u_mig_7series_0_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i) falls outside the operating range of the MMCM VCO frequency for this device (600.000 - 1200.000 MHz). The computed value is (CLKFBOUT_MULT_F * 1000 / (CLKINx_PERIOD * DIVCLK_DIVIDE)). Please run update_timing to update the MMCM settings. If that does not work, adjust either the input period CLKINx_PERIOD (40.000000), multiplication factor CLKFBOUT_MULT_F (8.000000) or the division factor DIVCLK_DIVIDE (1), in order to achieve a VCO frequency within the rated operating range for this device.
Looks like the internals of the Xilinx DDR3 module expects something different for the sys_clk_i and clk_ref_i frequencies. It suggests updating timing (Vivado wont allow me to do this), and setting the CLKIN1_PERIOD and other parameters manually is grayed out.
Any suggestions? I tried to do an example with Lucid following the tutorial, but that failed as well--it is getting confused what the top level file is--never finds it--and never builds.
Here's the top level source instantiation
mig_7series_0 i_mig_7series_0
(
.ddr3_dq (ddr3_dq),
.ddr3_dqs_n (ddr3_dqs_n),
.ddr3_dqs_p (ddr3_dqs_p),
.ddr3_addr (ddr3_addr),
.ddr3_ba (ddr3_ba),
.ddr3_ras_n (ddr3_ras_n),
.ddr3_cas_n (ddr3_cas_n),
.ddr3_we_n (ddr3_we_n),
.ddr3_reset_n (ddr3_reset_n),
.ddr3_ck_p (ddr3_ck_p),
.ddr3_ck_n (ddr3_ck_n),
.ddr3_cke (ddr3_cke),
.ddr3_cs_n (ddr3_cs_n),
.ddr3_dm (ddr3_dm),
.ddr3_odt (ddr3_odt),
.sys_clk_i (sysclk),
.clk_ref_i (sysclk_2x),
.app_addr (dev_ddr3_addr),
.app_cmd ({2'h0,~dev_ddr3_wr}),
.app_en (dev_ddr3_en),
.app_wdf_data (dev_ddr3_wdata),
.app_wdf_end (1),
.app_wdf_mask (0),
.app_wdf_wren (dev_ddr3_wr),
.app_rd_data (dev_ddr3_rdata),
.app_rd_data_end (1),
.app_rd_data_valid (dev_ddr3_rd_data_valid),
.app_rdy (dev_ddr3_rdy),
.app_wdf_rdy (dev_ddr3_wdf_rdy),
.app_sr_req (0),
.app_ref_req (0),
.app_zq_req (0),
.app_sr_active (dev_ddr3_sr_active),
.app_ref_ack (dev_ddr3_ref_ack),
.app_zq_ack (dev_ddr3_zq_ack),
.ui_clk (clk_ddr3_ui),
.ui_clk_sync_rst (ui_clk_sync_rst),
.init_calib_complete (init_calib_complete),
.device_temp (device_temp),
.sys_rst (nrst)
);
clk_wiz_0 i_clk_wiz_0
(
.reset (~nrst),
.clk_in1 (clk),
.clk_out1 (sysclk),
.clk_out2 (sysclk_2x),
.locked (locked)
);
https://alchitry.com/blogs/tutorials/usi...lchitry-au
and also just ran a pure verilog version on Vivado, neither one of which appears to work. Lot's of other stuff is working on this board, but I've had no luck with the DDR3.
I have the xilinx DDR3 module instantiated, along with a MMCM clock synthesis generating 100Mhz input, 100Mhz to sys_clk_i and 200Mhz to clk_ref_i. Vivado synthesizes without error, but routing DRC complains about this:
[DRC PDRC-34] MMCM_adv_ClkFrequency_div_no_dclk: The computed value 200.000 MHz (CLKIN1_PERIOD, net pll_clk3) for the VCO operating frequency of the MMCME2_ADV site MMCME2_ADV_X0Y2 (cell i_mig_7series_0/u_mig_7series_0_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i) falls outside the operating range of the MMCM VCO frequency for this device (600.000 - 1200.000 MHz). The computed value is (CLKFBOUT_MULT_F * 1000 / (CLKINx_PERIOD * DIVCLK_DIVIDE)). Please run update_timing to update the MMCM settings. If that does not work, adjust either the input period CLKINx_PERIOD (40.000000), multiplication factor CLKFBOUT_MULT_F (8.000000) or the division factor DIVCLK_DIVIDE (1), in order to achieve a VCO frequency within the rated operating range for this device.
Looks like the internals of the Xilinx DDR3 module expects something different for the sys_clk_i and clk_ref_i frequencies. It suggests updating timing (Vivado wont allow me to do this), and setting the CLKIN1_PERIOD and other parameters manually is grayed out.
Any suggestions? I tried to do an example with Lucid following the tutorial, but that failed as well--it is getting confused what the top level file is--never finds it--and never builds.
Here's the top level source instantiation
mig_7series_0 i_mig_7series_0
(
.ddr3_dq (ddr3_dq),
.ddr3_dqs_n (ddr3_dqs_n),
.ddr3_dqs_p (ddr3_dqs_p),
.ddr3_addr (ddr3_addr),
.ddr3_ba (ddr3_ba),
.ddr3_ras_n (ddr3_ras_n),
.ddr3_cas_n (ddr3_cas_n),
.ddr3_we_n (ddr3_we_n),
.ddr3_reset_n (ddr3_reset_n),
.ddr3_ck_p (ddr3_ck_p),
.ddr3_ck_n (ddr3_ck_n),
.ddr3_cke (ddr3_cke),
.ddr3_cs_n (ddr3_cs_n),
.ddr3_dm (ddr3_dm),
.ddr3_odt (ddr3_odt),
.sys_clk_i (sysclk),
.clk_ref_i (sysclk_2x),
.app_addr (dev_ddr3_addr),
.app_cmd ({2'h0,~dev_ddr3_wr}),
.app_en (dev_ddr3_en),
.app_wdf_data (dev_ddr3_wdata),
.app_wdf_end (1),
.app_wdf_mask (0),
.app_wdf_wren (dev_ddr3_wr),
.app_rd_data (dev_ddr3_rdata),
.app_rd_data_end (1),
.app_rd_data_valid (dev_ddr3_rd_data_valid),
.app_rdy (dev_ddr3_rdy),
.app_wdf_rdy (dev_ddr3_wdf_rdy),
.app_sr_req (0),
.app_ref_req (0),
.app_zq_req (0),
.app_sr_active (dev_ddr3_sr_active),
.app_ref_ack (dev_ddr3_ref_ack),
.app_zq_ack (dev_ddr3_zq_ack),
.ui_clk (clk_ddr3_ui),
.ui_clk_sync_rst (ui_clk_sync_rst),
.init_calib_complete (init_calib_complete),
.device_temp (device_temp),
.sys_rst (nrst)
);
clk_wiz_0 i_clk_wiz_0
(
.reset (~nrst),
.clk_in1 (clk),
.clk_out1 (sysclk),
.clk_out2 (sysclk_2x),
.locked (locked)
);