12-30-2020, 09:15 PM
Although it's alluded to, after searching the forum and internet too, I'm unable to find an example of changing the Au boards master clock speed through the on-board PLL.
For the projects I'm contemplating, it would be handy to multiply the clock by 150% and 200%. For another it's desirable to multiply the clock by 2/3 - that is multiply by 2, then divided by 3. The Xilinx App Note on Using Constraints hints at how to do this, however is not particularly straightforward, nor is it targeted at AL (which is understandable).
Any HOW-TO from the forum is appreciated.
MDL
- 100MHz on-board clock (can be multiplied internally by the FPGA)
For the projects I'm contemplating, it would be handy to multiply the clock by 150% and 200%. For another it's desirable to multiply the clock by 2/3 - that is multiply by 2, then divided by 3. The Xilinx App Note on Using Constraints hints at how to do this, however is not particularly straightforward, nor is it targeted at AL (which is understandable).
Any HOW-TO from the forum is appreciated.
MDL