I try to use DDR3 memory on the Au board for my project and it looks like the first read data get from the FSM I got after about 270nS. It related to about 22 cycles of ui_clk. Is it normal behave of DDR3 or have something wrong, please? I need accidently access to memory addresses for reading and writing by CPU without postponing of reading. Write is no critical because FIFO can be use, but read have to be fast (50ns is enough). Thanks for help.
The DDR3 read/write performance by its very nature is a bit unpredictable. 22 cycles doesn’t sound too bad to me for one read. Some will likely be faster.
The internal workings of the DDR3 controller are pretty complicated, but for a single random read, you need to close whatever row you had open, fetch the row you need to read from, then perform the read and wait for the response. This can also be delayed if the controller is performing a refresh cycle.
I’d recommend implementing some kind of cache to help mitigate this. There is a basic LRU cache in the components library in Alchitry Labs that can be used to speed up reads/writes to frequently used addresses. I used this with the GPU project to make it way more efficient.