The issue looks to be because you are trying to use 2D arrays as the input/output of your module but the constraint file is only 1D.
You actually can’t have ports that are 2D in Verilog so I’m surprised you didn’t get other errors about this.
The issue looks to be because you are trying to use 2D arrays as the input/output of your module but the constraint file is only 1D.
You actually can’t have ports that are 2D in Verilog so I’m surprised you didn’t get other errors about this.