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How to add "Block Design" created in Vivado
#1
I want to add a customized block memory module to my Alchitry Labs project (I'm using an Alchitry Au with Vivado tools).

When I used to use the Mojo IDE and Xilinx ISE tools, I could just open the Xilinix "Core Generator", from the "Tools" menu within Mojo IDE. Then, once I had finished generating the core, it would show up as a component in Mojo IDE.

Now, Vivado doesn't have "Core generator" it has "Block Designs" that you can add, but I don't know how to add one to my Alchitry Labs Project.

I can open the Vivado project that Alchitry Labs creates, and from there, I can generate block designs, but I can't add these to Alchitry Labs, and the next time I hit "Build Project", Alchitry Labs just deletes and re-generates the Vivado project entirely.

Am I supposed to create a separate Vivado project, generate blocks, and import them? I suspect this is not how to do it, but I can't even do this, because I think there is a bug in Alchitry Labs that doesn't let me import. Whenever I try to import a file, it pops up with an error saying that a project must be open to import a file, even when a project IS open. (I am using Windows 10, Alchitry Labs 1.0.4, see screenshot).
[Image: UpdsaxVY6Bc9FRsauGogWlbH4APUeVYDUbgKVuUC...24-h915-no]

Any help with how to add blocks generated from Vivado would be greatly appreciated. 
Cheers,

Rory
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#2
Hey Rory,

So let me start by saying this isn't technically supported yet.

That being said there is a workaround.

If it is just a .v file then you should be able to import it but I can confirm there is a bug there. I opened a bug report (https://github.com/alchitry/Alchitry-Labs/issues/12) and it should get fixed in the next version.

If it is more than that you can use the following work around.

Copy the base project (https://github.com/alchitry/Au-Base-Project) and generate whatever IP you want using Vivado.

In Vivado in the Sources panel under the IP Sources tab you can right click on an IP block and select "Enable Core Container." This will package it into a .wcix file (which is really just a zip file). You can find this file in project/project.srcs/sources_1/ip/block.wcix

In the Alchitry project directory make a  folder named "coreGen" and copy the .wcix file into it. You will also need to open the .wcix file and find the _stub.v file for the block. Alternatively you can use Vivado to open the file and copy paste it to a new file in the coreGen folder.

Open the project file (.alp) in a text editor.

In the <files> tag, you can add the ip with something like this.

Code:
    <core name="sqrt_calc">
      <src>sqrt_calc.xcix</src>
      <src>sqrt_calc_stub.v</src>
    </core>

Save the file and open your project. You should now see these under "Cores". The stub file is required so the project parser knows what the IP looks like. It's just an empty module with the inputs and outputs defined.

Some IP cores won't let you make them into a .wcix file (like the DDR3 interface). For those you can copy the whole IP directory into the coreGen folder and link to it like this.
Code:
    <core name="mig_7series_0">
      <src>mig</src>
      <src>mig/mig_7series_0.v</src>
    </core>

We will be working on adding real support for this soon.
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#3
Thanks heaps for that.

For anybody else: I can confirm this works (at least for IP that can be packaged in a .wcix file, I haven't tried the second option).
Also for anybody else: Just a couple of hints/problems I found along the way.

There is a small bug in Vivado v2018.3. If you follow the directions above exactly, Vivado will throw an error at you when you try to hit the "Enable Core Container" when you right click on the block/core/module/IP that you want to use.
"ERROR: [filemgmt 56-196] The Vivado project is inside the IP directory. You can not convert this IP to a core container."
Actually, you might just find that the  "Enable Core Container" is grayed out.

To fix this, start again with a new project or delete any cores that you have made. Then click the Project manager/settings tab in the left hand panel. Now check the box that says "Use core containers for IP". Now remake any block/core/IP that you want, and proceed as indicated in the above post.

One last thing:
To find the "[name_of_your_IP]_stub.v" file, make a copy of your "[name_of_your_IP].wcix", then rename it to "[name_of_your_IP].zip" and just extract it and find the file as indicated in the above post. (Don't put the copy of the .wcix file in the "coreGen" folder, I think this stopped my project from successfully building the first time round.)

Thanks again!
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