Clock Signals

[iggyglass]

Thanks for the reply! However because I'm using Alchitry Labs, I can't edit the .xdc files. I also tried opening the files up in an external editor (VS Code) and making the changes there however, it appears that when I build the project in Alchitry Labs, it overwrites the changes I made to the .xdc files and gives me the same error of

[Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets testClk_IBUF] >

[alchitry]

Thanks for helping out prebys!

To get around this, use a clock pin. Look at page 1 of the Au schematic. The positive side of a differential pairs with a name ending in "MRCC" can be used as global clocks. For example, if you change testClk to use pin B39 instead (which connect to pin D4 of the FPGA) it works. D4 is labeled as "IO_L12P_T1_MRCC_35" in the schematic which is a positive side pin (L12P) and a global clock pin (MRCC). 

The SRCC pins can be used as regional clocks, but you probably don't want this unless you know what you are doing.

[iggyglass]

Yep, that worked! Thanks for all of the help everyone!

[prebys]

Thanks for the reply! However because I'm using Alchitry Labs, I can't edit the .xdc files. I also tried opening the files up in an external editor (VS Code) and making the changes there however, it appears that when I build the project in Alchitry Labs, it overwrites the changes I made to the .xdc files and gives me the same error of

[Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets testClk_IBUF] >

It looks like you've found a workaround, but I've sometimes used pushbuttons as clocks when teaching initially teaching students about FPGAs, and you have to trick the compiler into letting it happen; however, I haven't tried it yet with Alchitry.

I *think* you can add custom XDC code to the au.xdc file in the contraints area, or add another .xdc file and it will get passed directly to Vivado verbatim, but I admit I haven't tried it yet.