Currently the only way that I can think of to utilize simulations, for Lucid or Verilog, is to either, import the transpiled (or native) Verilog code into Vivado, then write my test bench there for simulation purposes. This is sorta clunky, but the simulations are very useful for more complex designs.
Is there any future plans to implement some sort of simulation process into Alchitry Labs, or is this going to be the normal process?