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Cu Demo Project fails to build with IceStorm
Using Alchitry Labs 1.0.3 on Linux using the ubuntu-provided IceStorm packages (fpga-icestorm et al).

I had the IDE create a new Lucid "Cu IO Element Demo" project and built it.

It fails with:


Finished synthesis.

Project IceStorm doesn't support .sdc constraints. "/home/.../CuDemo/work/constraint/alchitry.sdc" will be ignored.
seed: 1
device: 8k
read_chipdb +/share/arachne-pnr/chipdb-8k.bin...
 supported packages: cb132, cb132:4k, cm121, cm121:4k, cm225, cm225:4k, cm81, cm81:4k, ct256, tq144:4k
read_blif /home/.../CuDemo/work/alchitry.blif...
read_pcf /home/.../CuDemo/work/constraint/alchitry.pcf...
fatal error: $_TBUF_ gate must drive top-level output or inout port

Finished placement.
Error: Failed to open input file.

Bin file (/home/.../CuDemo/work/alchitry.bin) could not be found! The build probably failed.
Did you check if all inputs and outputs are assigned correctly?

"fatal error: $_TBUF_ gate must drive top-level output or inout port"

sounds like your .blif file wants to drive something the wrong way.
This is the default project shipped with the alchitry-labs IDE, so I would have expected it to work unchanged.
Maybe this is the issue: https://github.com/YosysHQ/arachne-pnr/issues/112

What version of yosys and arachne-pnr are installed?

Sadly I cannot test as I don't know how to pass lucid to yosys (Alchitry-Labs does not run on my machine). If you have the converted Verilog (*.v) I could test with my version.
Ubuntu 18.04

fpga-icestorm 0~20160913git266e758-3
fpga-icestorm-chipdb 0~20160913git266e758-3
yosys 0.7-2  (changelog.Debian shows last update on 2016-Nov-06)
arachne-pnr 0.1+20160813git52e69ed-1
arachne-pnr-chipdb 0.1+20160813git52e69ed-1

$ yosys -V
Yosys 0.7 (git sha1 61f6811, gcc 6.2.0-11ubuntu1 -O2 -fdebug-prefix-map=/build/yosys-OIL3SR/yosys-0.7=. -fstack-protector-strong -fPIC -Os)

$ arachne-pnr -v
arachne-pnr 0.1+20151224git1a4fdf9 (git sha1 1a4fdf9, g++ 6.2.0-10ubuntu1 -O2 -fdebug-prefix-map=/build/arachne-pnr-8ETCVz/arachne-pnr-0.1+20160813git52e69ed=. -fPIE -fstack-protector-strong)
Attached the alchitry-labs generated "work" directory:
.tar   CuDemo_work.tar (Size: 120 KB / Downloads: 56)
I tried with different newer versions of yosys and arachne-pnr.

The result is the same:

Quote:alchitry.blif:1781: fatal error: toplevel inout port 'io_dip[0]' connected to tristate buffer and driving a net

On the 35C3 congress I heard that arachne-pnr is superseded by nextpnr so I tried to build with it. And it seems to be successful. I did not had the time to test. But there is an bitstream (see attachment (named .txt as else not accepted)).

What I did to build (In the work directory):

yosys -p 'synth_ice40 -top cu_top_0 -json alchitry.json' verilog/*.v
cat constraint/*.pcf > all.pcf
nextpnr-ice40 --hx8k --package cb132 --json alchitry.json  --pcf all.pcf  --asc alchitry.asc
icepack alchitry.asc alchitry.bin

The toolchain I had to compile by hand:

Sadly this is not a comfortable way for unexperienced users. As this toolchain is very new you have to expect some issues.

I will try the bitstream later (I hope there is something to see without the shield).


Attached Files
.txt   alchitry.txt (Size: 131.93 KB / Downloads: 56)
As far as I can test with just the basic Cu board it worked. It wasn't anything on the LEDs but the programmed loop of the serial bus responded.

I tested that with python:
>>> from pylibftdi import Device;
>>> device = Device(interface_select=2)
>>> device.flush()
>>> device.flush()
>>> device.write("a")
>>> device.read(1)
The IO example doesn't build for me under IceStorm either although I get a different error during synthesis. I haven't had a chance to figure out what's going on.

It does build and work under IceCube.

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