02-21-2020, 04:45 AM
Just finished making a set of constraint files for using the AU on vivado since I could not find any for the life of me.
One file is for the bare Au (and breakout board Bu). The other file is for the Io shield. It works hand-in-hand with the Au xdc (Ie it does not have the clock or reset button defined in it.)
One thing to note is that the DDR3 definitions are untested and 90% sure they are incorrect. I have been working on these files for hours now and am too tired to look at what their IOSTANDARD values should be in the datasheets. The port locations and the labels are correct however. One day I'll update it to the correct IOSTANDARD values but that day is not today....
The IO shield has all of its inputs pulled down to ground via the fpga's internal pulldowns.
One file is for the bare Au (and breakout board Bu). The other file is for the Io shield. It works hand-in-hand with the Au xdc (Ie it does not have the clock or reset button defined in it.)
One thing to note is that the DDR3 definitions are untested and 90% sure they are incorrect. I have been working on these files for hours now and am too tired to look at what their IOSTANDARD values should be in the datasheets. The port locations and the labels are correct however. One day I'll update it to the correct IOSTANDARD values but that day is not today....
The IO shield has all of its inputs pulled down to ground via the fpga's internal pulldowns.