Just finished making a set of constraint files for using the AU on vivado since I could not find any for the life of me.
One file is for the bare Au (and breakout board Bu). The other file is for the Io shield. It works hand-in-hand with the Au xdc (Ie it does not have the clock or reset button defined in it.)
One thing to note is that the DDR3 definitions are untested and 90% sure they are incorrect. I have been working on these files for hours now and am too tired to look at what their IOSTANDARD values should be in the datasheets. The port locations and the labels are correct however. One day I’ll update it to the correct IOSTANDARD values but that day is not today…
The IO shield has all of its inputs pulled down to ground via the fpga’s internal pulldowns.
There was a post made some time ago about making a board file for the AU https://forum.alchitry.com/thread-69.html . Unfortunately it didn’t work for me nor did Vivado’s hardware manager pick up the board. Can you tell us if Vivado can generate a bitstream and upload it to the board?
I can generate a bitstream successfully. Uploading from vivado is not possible due to how the board is designed currently. That’s the next project. You can generate the bitstream and upload it using alchitry loader.
The only issue I’ve found so far besides the ddr3 is led12 is giving issues. I’ll look into it later.
then my IO_LED[10] was just permanently off, so I did the same for IO_LED[10]
set_property PACKAGE_PIN E2 [get_ports IO_LED[10]]
set_property IOSTANDARD LVCMOS33 [get_ports {IO_LED[10]}]
Following the schematics, I found L11 (IO_LED[10]) is on pin 6 of the bank B connector, which is B2, so I changed the above to;