• 0 Vote(s) - 0 Average
  • 1
  • 2
  • 3
  • 4
  • 5
Alchitry Au - IP and such..
#5
PWM works great.
To make the PWM wave in the Au using Verilog.
Follow the online tutorial at https://alchitry.com/blogs/tutorials/pul...modulation
and copy the led_wave.v module from the tutorial as a new Verilog Source in Alchitry Labs.
Modify the au_top.v to instantiate the led_wave module and build the project.
(Note: I added the Io's io_leds to a new Constrainsts file called io_led.acf)

module au_top(
input clk, // 100Mhz clock
input rst_n, // reset button (active low)
output [7:0] led, // 8 user controllable LEDs
input usb_rx, // USB->Serial input
output usb_tx, // USB->Serial output
output [23:0] io_led // LEDs on IO Shield
);

wire rst;

// The reset conditioner is used to synchronize the reset signal to the FPGA
// clock. This ensures the entire FPGA comes out of reset at the same time.
reset_conditioner reset_conditioner(
.clk(clk),
.in(!rst_n),
.out(rst)
);

led_wave wave (
.rst(rst),
.clk(clk),
.led(led)
);

assign io_led = 24'h000000; // turn LEDs off

assign usb_tx = usb_rx; // echo the serial data

endmodule
  Reply


Messages In This Thread
RE: Alchitry Au - IP and such.. - by prebys - 01-08-2020, 09:49 PM
RE: Alchitry Au - IP and such.. - by prebys - 01-09-2020, 07:47 PM
RE: Alchitry Au - IP and such.. - by MichaelTuckwell - 01-10-2020, 01:07 AM

Forum Jump:


Users browsing this thread: 1 Guest(s)