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Some confusion about Au DDR3 interface
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So the data bus is only 16 bits wide but the DDR3 controller always operates in bursts of 8 so you end up with the last three address bits being 0 and reading/writing in 128 bit chunks. This is a design choice of the controller and not a restriction of the DDR3 itself.

This means each of the addresses excluding the last three bits are 16 bytes wide. This gives you 2^24 addresses as you pointed out. The MSB is always 0 since it corresponds to the "bank" which is used when you have multiple DDR3 chips.
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RE: Some confusion about Au DDR3 interface - by alchitry - 01-14-2021, 03:07 PM

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