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DDR3 speed of READ command
The DDR3 read/write performance by its very nature is a bit unpredictable. 22 cycles doesn't sound too bad to me for one read. Some will likely be faster.

The internal workings of the DDR3 controller are pretty complicated, but for a single random read, you need to close whatever row you had open, fetch the row you need to read from, then perform the read and wait for the response. This can also be delayed if the controller is performing a refresh cycle.

I'd recommend implementing some kind of cache to help mitigate this. There is a basic LRU cache in the components library in Alchitry Labs that can be used to speed up reads/writes to frequently used addresses. I used this with the GPU project to make it way more efficient.

Messages In This Thread
DDR3 speed of READ command - by LMN128 - 11-09-2020, 01:05 PM
RE: DDR3 speed of READ command - by alchitry - 07-22-2021, 02:27 PM

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