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I/O Magic on Au and VHDL
I just got a brand new shiny Au two days ago, along with an IO element and a breadboard shield, and I was going through the first couple of Tutorial examples over the weekend, which worked all fine.  But I am afraid, I don't quite understand them, or more precisely, the stuff that goes on behind the scenes.  To begin with, I have no experience or knowledge in Verilog at all, and even less in Lucid - I do know some VHDL though.  

Here is what I don't understand: Who sits on top of the au_top model in Verilog and knows where to route the clk and the rst_n signals, as well as the led vector and the usb_rc and usb_tx signals to?  There must be some correspondence to the physical signals on the board - where is that defined?  And how would I define those if I were to try to convert the tutorials to VHDL, which I would very much like to do to gain some familiarity back? Huh  Where can I find out about these things to read up on?

Messages In This Thread
I/O Magic on Au and VHDL - by Ekkehard - 02-23-2020, 11:18 PM
RE: I/O Magic on Au and VHDL - by Ekkehard - 02-26-2020, 07:40 PM
RE: I/O Magic on Au and VHDL - by Ekkehard - 02-27-2020, 05:43 PM

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