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IO element Constraints Broken in Vivado
Hi everyone. New user to the forum as well as FPGAs. I'm hoping someone can help me solve this issue before I tear my hair out... and forgive me if this is an obvious issue, as this is my first time working with an FPGA.

So the issue that I'm having is that Vivado doesn't seem to want to synthesize my design after I tried to ad the IO element constraints to my project. I came across this thread here for generating an XDC constraint for the IO element "shield", but Vivado seems to not like this file at all. I keep getting the error "[Common 17-55] 'set_property' expects at least one object" for nearly every single line (lines 7+), and "[Common 17-69] Command failed: Site cannot be assigned to more than one port" for the lines 1,3,5.

I've attached my au.top and io.xdc for reference. Thanks for helping a n00b out.

Attached Files
.txt   io.txt (Size: 8.63 KB / Downloads: 14)
.txt   au_top.txt (Size: 813 bytes / Downloads: 6)
The issue looks to be because you are trying to use 2D arrays as the input/output of your module but the constraint file is only 1D.

You actually can't have ports that are 2D in Verilog so I'm surprised you didn't get other errors about this.

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