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MOJO sdram - Printable Version

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MOJO sdram - alialaei - 10-18-2021

Hi everyone.
I have designed a new SDRAM shield for my own mojo board(with exactly the same SDRAM chip).
with two differences in comparison to the original SDRAM shield.

1. I did take it easy and didn't consider high-frequency PCB design stuff(no length matching) I think 100MHz isn't that high, is it?
2. due to some other considerations I've changed some pins:
      sdram_cs        from P115 to P118
      sdram_we       from P111 to P121
      sdram_cas      from P112 to P120
      sdram_ras      from P114 to P119
      sdram_ba<0> from P116 to P117
      sdram_ba<1> from P117 to P116
      sdram_a<0>  from P118 to P115
      sdram_a<1>  from P119 to P114
      sdram_a<2>  from P120 to P112
      sdram_a<3>  from P121 to P111
it means they are two-by-two changed as below:
P115  <> P118
P121  <> P111
P120  <> P112
P114  <> P119
P116  <> P117


mojo SDRAM test example with modified UCF does not work. (It acts as there is no SDRAM-shield on Mojo board)

Do you think what could be the cause of the problem?
Is 100 Mhz considered high such that could cause this problem? (I even reduced the clock but no achievement)

or could changing pins cause this problem?

ThanksSmile


RE: MOJO sdram - tistructor - 10-20-2021

I also made an 8bit and 16bit 100MHz sdram shield.
The test program in lucid does not work and I did not understand why.
If you try the test program in verilog this works and the leds light up correctly.

I used the same pins as the original card.

I haven't tested with the sdram for some time.
I had done a code conversion to use 16-bit chips in lucid but was unable to get it to work.
When I have time I do the code conversion for verilog.


RE: MOJO sdram - alialaei - 10-20-2021

(10-20-2021, 08:36 AM)tistructor Wrote: I also made an 8bit and 16bit 100MHz sdram shield.
The test program in lucid does not work and I did not understand why.
If you try the test program in verilog this works and the leds light up correctly.

I used the same pins as the original card.

I haven't tested with the sdram for some time.
I had done a code conversion to use 16-bit chips in lucid but was unable to get it to work.
When I have time I do the code conversion for verilog.

Intriguing problems!
Did you consider high-frequency stuff like length matching?
Have you played with the delay value(which is 100 by default)?
I guess this value could depend on PCB design (+routing in FPGA; we can't be sure RTL design is exactly the same) as well working frequency, am I right?

Note: Despite I used some other values, no success is achieved but I thought changing this value might help.


RE: MOJO sdram - tistructor - 10-22-2021

Try the example in verilog.


RE: MOJO sdram - alialaei - 11-02-2021

(10-22-2021, 10:51 PM)tistructor Wrote: Try the example in verilog.

I've tried both, nothing differs...