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Au plus and DDR3 Tutorial - Printable Version

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Au plus and DDR3 Tutorial - howdyrichard - 07-07-2021

It will not create the Stub file whether I use the above zip or the Au code (same results). I am using Au+. This is the error in Vivado: mig_7series_0_synth_1, Synthesis Out-of-date. Under Chang Log there are 5 errors, netlist.v are and stub.v are two of them. I did fid an article on how to make out of date be ignored but due to upgrades since 2018 I cannot find how to do it.

I saw somewhere that if a Au+ board is used then a stub file is not required.  I cannot get past the Synthesis Out-of-date error.  Anyone know the solution to this?  I am using Vivado 2020.2.

Thank you!

RE: Au plus and DDR3 Tutorial - howdyrichard - 07-31-2021

So why am I buying into Alchitry? 

The tutorials go so far and then the examples run into problems as they are not being updated, apparently.  I asked what I found out to be a problem with others as well and no support. 

I've spent over $200 on this one project and was told that the Au Plus will work the same an Au (just more I/O and capabilities) which was unavailable at the time.  Now I can't get through the DDR3 tutorial because of out-dated software.

It's probably fixable, maybe, I guess if I could get a little push from some talent here!

Thank you,

RE: Au plus and DDR3 Tutorial - Tyrving - 08-07-2021

Hey howdyrichard,
I really wish I could be of more help, but at this point your best hope is that Justin will solve this next time he checks the forums. The only idea I have is to try install all the software version that were current at the making of the tutorial - but considering as the AU+ was released long after said tutorial was written, I doubt much will come of this.

Best of luck,

RE: Au plus and DDR3 Tutorial - howdyrichard - 08-07-2021

Thanks for at least replying!!! Maybe someone at Xilinx can help...I will look forward to Justin if he cares to undertake the effort.

RE: Au plus and DDR3 Tutorial - alchitry - 09-24-2021

I don't quite follow where you are getting the error. Is this in Alchitry Labs when you are trying to add the MIG core?

Is it during the MIG core synthesis?