Alchitry Forums
Au plus and DDR3 Tutorial - Printable Version

+- Alchitry Forums (https://forum.alchitry.com)
+-- Forum: Alchitry (https://forum.alchitry.com/forum-1.html)
+--- Forum: General Questions (https://forum.alchitry.com/forum-2.html)
+--- Thread: Au plus and DDR3 Tutorial (/thread-352.html)



Au plus and DDR3 Tutorial - howdyrichard - 07-07-2021

It will not create the Stub file whether I use the above zip or the Au code (same results). I am using Au+. This is the error in Vivado: mig_7series_0_synth_1, Synthesis Out-of-date. Under Chang Log there are 5 errors, netlist.v are and stub.v are two of them. I did fid an article on how to make out of date be ignored but due to upgrades since 2018 I cannot find how to do it.

I saw somewhere that if a Au+ board is used then a stub file is not required.  I cannot get past the Synthesis Out-of-date error.  Anyone know the solution to this?  I am using Vivado 2020.2.

Thank you!


RE: Au plus and DDR3 Tutorial - howdyrichard - 07-31-2021

So why am I buying into Alchitry? 

The tutorials go so far and then the examples run into problems as they are not being updated, apparently.  I asked what I found out to be a problem with others as well and no support. 

I've spent over $200 on this one project and was told that the Au Plus will work the same an Au (just more I/O and capabilities) which was unavailable at the time.  Now I can't get through the DDR3 tutorial because of out-dated software.

It's probably fixable, maybe, I guess if I could get a little push from some talent here!

Thank you,
howdyrichard


RE: Au plus and DDR3 Tutorial - Tyrving - 08-07-2021

Hey howdyrichard,
I really wish I could be of more help, but at this point your best hope is that Justin will solve this next time he checks the forums. The only idea I have is to try install all the software version that were current at the making of the tutorial - but considering as the AU+ was released long after said tutorial was written, I doubt much will come of this.

Best of luck,
Mark


RE: Au plus and DDR3 Tutorial - howdyrichard - 08-07-2021

Thanks for at least replying!!! Maybe someone at Xilinx can help...I will look forward to Justin if he cares to undertake the effort.


RE: Au plus and DDR3 Tutorial - alchitry - 09-24-2021

I don't quite follow where you are getting the error. Is this in Alchitry Labs when you are trying to add the MIG core?

Is it during the MIG core synthesis?


RE: Au plus and DDR3 Tutorial - JohnGreenCloG - 10-29-2021

I also can't figure out where you get the error?


RE: Au plus and DDR3 Tutorial - howdyrichard - 12-28-2021

Sorry this took so long and I am back on it.  I really want to learn this thing, now more than ever!
Found the errors while "Adding Memory Controller" using Vivado 2020.2 as recommended:  

ERROR: [Synth 8-729] Failed to open 'C:/Users/howdy/Documents/Alchitry/alchitry-labs-1.2.5-windows/alchitry-labs-1.2.5/library/base/alchitry-au-plus/Lucid/DDR/cores/managed_ip_project/managed_ip_project.runs/mig_7series_0_synth_1/.Xil/Vivado-7144-ASTRO//incrSyn/3772560790/u/g//global_name.straps.rtd': No such file or directory
ERROR: [Synth 8-787] cannot access rtd files in 'C:/Users/howdy/Documents/Alchitry/alchitry-labs-1.2.5-windows/alchitry-labs-1.2.5/library/base/alchitry-au-plus/Lucid/DDR/cores/managed_ip_project/managed_ip_project.runs/mig_7series_0_synth_1/.Xil/Vivado-7144-ASTRO/realtime/tmp//', this is a FATAL ERROR! Please make sure the directory is readable and writable by the program and do not delete files from this directory while the program is running.
ERROR: [Synth 8-787] cannot access rtd files in 'C:/Users/howdy/Documents/Alchitry/alchitry-labs-1.2.5-windows/alchitry-labs-1.2.5/library/base/alchitry-au-plus/Lucid/DDR/cores/managed_ip_project/managed_ip_project.runs/mig_7series_0_synth_1/.Xil/Vivado-7144-ASTRO/realtime/tmp//', this is a FATAL ERROR! Please make sure the directory is readable and writable by the program and do not delete files from this directory while the program is running.
An unrecoverable error has occurred, synthesis cancelled.
TclStackFree: incorrect freePtr. Call out of sequence?
[Tue Dec 28 07:39:23 2021] mig_7series_0_synth_1 finished
WARNING: [Vivado 12-8222] Failed run(s) : 'mig_7series_0_synth_1'
--------------------------------------------------------------------------------------------------------------------------------
The first error, the path is good until: global_name.straps.rtd
The next two errors, the path is good until: realtime/tmp, but there is nothing in tmp.
--------------------------------------------------------------------------------------------------------------------------------
I also tried 2021.2.

I do have a copy of the stub.v file from Xilinx website but I do not know how to add it to cores directory in Alchitry.  As it stands, it only had the .xci and because the io tags are not listed here there are numerous errors in the wrapper and au_plus_top.

*** I downloaded Vivado 2016.1 and it created the stub file ***
I hope this helps others!  I have wasted days on the tutorial recommendation to use 2020.2 or higher!!!