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AU - DDR3 PIn use - Printable Version

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AU - DDR3 PIn use - TechPaula - 05-09-2021

I'm having some problems running the "memory interface generator" in vivado.
I'm trying to configure the DDR3 basic on the schematic and XDC files, however I get an error;

Code:
ERROR : The port ddr3_addr[5] is allocated in the bank 15 where the input ports are allocated. Enable the Internal Vref to use the Vref as GPIO.

now I believe, I need these lines;
Code:
set_property INTERNAL_VREF 0.7 [get_iobanks 65]
set_property INTERNAL_VREF 0.84 [get_iobanks 67]
but with those in the projects XDC file and with the project built, I still get the error.

I've tried this thread - https://forum.alchitry.com/thread-234.html
But sadly the project that is created is blank and has no mig_7series_0 module.

Could you explain how to configure this to work please?


RE: AU - DDR3 PIn use - alchitry - 05-18-2021

The easiest way to bypass all this is to use Alchitry Labs and choose Project->Add Memory Controller. This will automatically configure it correctly.

If you want to do this outside Alchitry Labs, you can download the mig project file here https://github.com/alchitry/Alchitry-Labs/blob/master/library/components/mig.prj

You can use this with the Vivado IP Catalog to generate a MIG core.

You may also need the following pinout file when creating the core. https://cdn.alchitry.com/forum/mig_7series_0.xdc