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Clock Signals - Printable Version

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Clock Signals - iggyglass - 03-21-2019

Hey, so while I was working on a project, I noticed that if I wanted to use an external input as the clock signal of a dff:
Code:
.clk(exampleInput), .rst(rst) {
  dff example;
}
it fails to compile and gives me the bin file not found error. 

I was wondering if there was any way to do this, or if this is a bug, or what.

Thanks,
iggyglass


RE: Non-clock clock signals - alchitry - 03-21-2019

This is generally a terrible idea if exampleInput isn't a clock. If it is you need to specify it in the constraint files. The error in the builder output would also be helpful.

You can describe what you are trying to do so I can offer an alternative?


RE: Non-clock clock signals - iggyglass - 03-21-2019

Ah Ok. I didn't realize that you could specify a clock signal in the constraint files. What is the syntax for it?


RE: Clock Signals - iggyglass - 03-22-2019

So now I've edited the constraints file so that exampleInput is defined as the following:
Code:
clock exampleInput 50MHz;
Yet it still fails to compile saying that au_top_0.bin could not be found.

Here is what my au_top.luc file looks like:
Code:
module au_top (
   input clk,              // 100MHz clock
   input rst_n,            // reset button (active low)
   input testClk,          // clock for testing
   input testIn,           // input for test dff
   input usb_rx,           // USB->Serial input
   output usb_tx,          // USB->Serial output
   output led [8]          // 8 user controllable LEDs
) {
 
 sig rst;                  // reset signal
 
 .clk(clk) {
   // The reset conditioner is used to synchronize the reset signal to the FPGA
   // clock. This ensures the entire FPGA comes out of reset at the same time.
   reset_conditioner reset_cond;
 }
 
 .clk(testClk), .rst(rst) {
   dff testdff;
 }
 
 always {
   reset_cond.in = ~rst_n; // input raw inverted reset signal
   rst = reset_cond.out;   // conditioned reset
   
   led[7:1] = 0;           // turn LEDs off

   usb_tx = usb_rx;        // echo the serial data
   
   testdff.d = testIn;
   led[0] = testdff.q;
 }
}
So, I'm wondering what I'm doing wrong.


RE: Clock Signals - alchitry - 03-22-2019

Can you post the full build output?


RE: Clock Signals - iggyglass - 03-22-2019

Sure, here it is:
Code:
****** Vivado v2018.3 (64-bit)
 **** SW Build 2405991 on Thu Dec  6 23:38:27 MST 2018
 **** IP Build 2404404 on Fri Dec  7 01:43:56 MST 2018
   ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.

source {C:\Users\iggyg\OneDrive\Documents\alchitry\DeleteMeErrorTest\work\project.tcl}
# set projDir "C:/Users/iggyg/OneDrive/Documents/alchitry/DeleteMeErrorTest/work/vivado"
# set projName "DeleteMeErrorTest"
# set topName top
# set device xc7a35tftg256-1
# if {[file exists "$projDir/$projName"]} { file delete -force "$projDir/$projName" }
# create_project $projName "$projDir/$projName" -part $device
INFO: [ProjectBase 1-489] The host OS only allows 260 characters in a normal path. The project is stored in a path with more than 80 characters. If you experience issues with IP, Block Designs, or files not being found, please consider moving the project to a location with a shorter path. Alternately consider using the OS subst command to map part of the path to a drive letter.
Current project path is 'C:/Users/iggyg/OneDrive/Documents/alchitry/DeleteMeErrorTest/work/vivado/DeleteMeErrorTest'
# set_property design_mode RTL [get_filesets sources_1]
# set verilogSources [list "C:/Users/iggyg/OneDrive/Documents/alchitry/DeleteMeErrorTest/work/verilog/au_top_0.v" "C:/Users/iggyg/OneDrive/Documents/alchitry/DeleteMeErrorTest/work/verilog/reset_conditioner_1.v"]
# import_files -fileset [get_filesets sources_1] -force -norecurse $verilogSources
# set xdcSources [list "C:/Users/iggyg/OneDrive/Documents/alchitry/DeleteMeErrorTest/work/constraint/testclksig.xdc" "C:/Program\ Files/Alchitry/Alchitry\ Labs/library/components/au.xdc" "C:/Users/iggyg/OneDrive/Documents/alchitry/DeleteMeErrorTest/work/constraint/alchitry.xdc" ]
# read_xdc $xdcSources
# set_property STEPS.WRITE_BITSTREAM.ARGS.BIN_FILE true [get_runs impl_1]
# update_compile_order -fileset sources_1
# launch_runs -runs synth_1 -jobs 8
[Fri Mar 22 13:07:57 2019] Launched synth_1...
Run output will be captured here: C:/Users/iggyg/OneDrive/Documents/alchitry/DeleteMeErrorTest/work/vivado/DeleteMeErrorTest/DeleteMeErrorTest.runs/synth_1/runme.log
# wait_on_run synth_1
[Fri Mar 22 13:07:57 2019] Waiting for synth_1 to finish...

*** Running vivado
   with args -log au_top_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source au_top_0.tcl


****** Vivado v2018.3 (64-bit)
 **** SW Build 2405991 on Thu Dec  6 23:38:27 MST 2018
 **** IP Build 2404404 on Fri Dec  7 01:43:56 MST 2018
   ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.

source au_top_0.tcl -notrace
Command: synth_design -top au_top_0 -part xc7a35tftg256-1
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35t'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t'
INFO: Launching helper process for spawning children vivado processes
INFO: Helper process launched with PID 5608
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 361.793 ; gain = 100.965
---------------------------------------------------------------------------------
INFO: [Synth 8-6157] synthesizing module 'au_top_0' [C:/Users/iggyg/OneDrive/Documents/alchitry/DeleteMeErrorTest/work/vivado/DeleteMeErrorTest/DeleteMeErrorTest.srcs/sources_1/imports/verilog/au_top_0.v:7]
INFO: [Synth 8-6157] synthesizing module 'reset_conditioner_1' [C:/Users/iggyg/OneDrive/Documents/alchitry/DeleteMeErrorTest/work/vivado/DeleteMeErrorTest/DeleteMeErrorTest.srcs/sources_1/imports/verilog/reset_conditioner_1.v:11]
    Parameter STAGES bound to: 3'b100
INFO: [Synth 8-6155] done synthesizing module 'reset_conditioner_1' (1#1) [C:/Users/iggyg/OneDrive/Documents/alchitry/DeleteMeErrorTest/work/vivado/DeleteMeErrorTest/DeleteMeErrorTest.srcs/sources_1/imports/verilog/reset_conditioner_1.v:11]
INFO: [Synth 8-6155] done synthesizing module 'au_top_0' (2#1) [C:/Users/iggyg/OneDrive/Documents/alchitry/DeleteMeErrorTest/work/vivado/DeleteMeErrorTest/DeleteMeErrorTest.srcs/sources_1/imports/verilog/au_top_0.v:7]
WARNING: [Synth 8-3917] design au_top_0 has port led[7] driven by constant 0
WARNING: [Synth 8-3917] design au_top_0 has port led[6] driven by constant 0
WARNING: [Synth 8-3917] design au_top_0 has port led[5] driven by constant 0
WARNING: [Synth 8-3917] design au_top_0 has port led[4] driven by constant 0
WARNING: [Synth 8-3917] design au_top_0 has port led[3] driven by constant 0
WARNING: [Synth 8-3917] design au_top_0 has port led[2] driven by constant 0
WARNING: [Synth 8-3917] design au_top_0 has port led[1] driven by constant 0
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 418.035 ; gain = 157.207
---------------------------------------------------------------------------------

Report Check Netlist:
+------+------------------+-------+---------+-------+------------------+
|      |Item              |Errors |Warnings |Status |Description       |
+------+------------------+-------+---------+-------+------------------+
|1     |multi_driven_nets |      0|        0|Passed |Multi driven nets |
+------+------------------+-------+---------+-------+------------------+
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 418.035 ; gain = 157.207
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 418.035 ; gain = 157.207
---------------------------------------------------------------------------------
INFO: [Device 21-403] Loading part xc7a35tftg256-1
INFO: [Project 1-570] Preparing netlist for logic optimization

Processing XDC Constraints
Initializing timing engine
Parsing XDC File [C:/Users/iggyg/OneDrive/Documents/alchitry/DeleteMeErrorTest/work/constraint/testclksig.xdc]
Finished Parsing XDC File [C:/Users/iggyg/OneDrive/Documents/alchitry/DeleteMeErrorTest/work/constraint/testclksig.xdc]
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [C:/Users/iggyg/OneDrive/Documents/alchitry/DeleteMeErrorTest/work/constraint/testclksig.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/au_top_0_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/au_top_0_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Parsing XDC File [C:/Program Files/Alchitry/Alchitry Labs/library/components/au.xdc]
Finished Parsing XDC File [C:/Program Files/Alchitry/Alchitry Labs/library/components/au.xdc]
Parsing XDC File [C:/Users/iggyg/OneDrive/Documents/alchitry/DeleteMeErrorTest/work/constraint/alchitry.xdc]
Finished Parsing XDC File [C:/Users/iggyg/OneDrive/Documents/alchitry/DeleteMeErrorTest/work/constraint/alchitry.xdc]
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [C:/Users/iggyg/OneDrive/Documents/alchitry/DeleteMeErrorTest/work/constraint/alchitry.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/au_top_0_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/au_top_0_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 691.859 ; gain = 0.000
Completed Processing XDC Constraints

Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 691.859 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 691.859 ; gain = 0.000
Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.012 . Memory (MB): peak = 691.859 ; gain = 0.000
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 691.859 ; gain = 431.031
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7a35tftg256-1
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 691.859 ; gain = 431.031
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 691.859 ; gain = 431.031
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 691.859 ; gain = 431.031
---------------------------------------------------------------------------------

Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start RTL Component Statistics
---------------------------------------------------------------------------------
Detailed RTL Component Info :
+---Registers :
                    4 Bit    Registers := 1    
                    1 Bit    Registers := 1    
---------------------------------------------------------------------------------
Finished RTL Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Hierarchical Component Statistics
---------------------------------------------------------------------------------
Hierarchical RTL Component report
Module au_top_0
Detailed RTL Component Info :
+---Registers :
                    1 Bit    Registers := 1    
Module reset_conditioner_1
Detailed RTL Component Info :
+---Registers :
                    4 Bit    Registers := 1    
---------------------------------------------------------------------------------
Finished RTL Hierarchical Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 90 (col length:60)
BRAMs: 100 (col length: RAMB18 60 RAMB36 30)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
Warning: Parallel synthesis criteria is not met
WARNING: [Synth 8-3917] design au_top_0 has port led[7] driven by constant 0
WARNING: [Synth 8-3917] design au_top_0 has port led[6] driven by constant 0
WARNING: [Synth 8-3917] design au_top_0 has port led[5] driven by constant 0
WARNING: [Synth 8-3917] design au_top_0 has port led[4] driven by constant 0
WARNING: [Synth 8-3917] design au_top_0 has port led[3] driven by constant 0
WARNING: [Synth 8-3917] design au_top_0 has port led[2] driven by constant 0
WARNING: [Synth 8-3917] design au_top_0 has port led[1] driven by constant 0
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 691.859 ; gain = 431.031
---------------------------------------------------------------------------------

Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 728.582 ; gain = 467.754
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 728.582 ; gain = 467.754
---------------------------------------------------------------------------------

Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 738.109 ; gain = 477.281
---------------------------------------------------------------------------------

Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 738.109 ; gain = 477.281
---------------------------------------------------------------------------------

Report Check Netlist:
+------+------------------+-------+---------+-------+------------------+
|      |Item              |Errors |Warnings |Status |Description       |
+------+------------------+-------+---------+-------+------------------+
|1     |multi_driven_nets |      0|        0|Passed |Multi driven nets |
+------+------------------+-------+---------+-------+------------------+
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 738.109 ; gain = 477.281
---------------------------------------------------------------------------------

Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 738.109 ; gain = 477.281
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 738.109 ; gain = 477.281
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 738.109 ; gain = 477.281
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 738.109 ; gain = 477.281
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------

Report BlackBoxes:
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+

Report Cell Usage:
+------+-----+------+
|      |Cell |Count |
+------+-----+------+
|1     |BUFG |     2|
|2     |LUT1 |     1|
|3     |FDRE |     1|
|4     |FDSE |     4|
|5     |IBUF |     5|
|6     |OBUF |     9|
+------+-----+------+

Report Instance Areas:
+------+-------------+--------------------+------+
|      |Instance     |Module              |Cells |
+------+-------------+--------------------+------+
|1     |top          |                    |    22|
|2     |  reset_cond |reset_conditioner_1 |     5|
+------+-------------+--------------------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 738.109 ; gain = 477.281
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 7 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:14 ; elapsed = 00:00:19 . Memory (MB): peak = 738.109 ; gain = 203.457
Synthesis Optimization Complete : Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 738.109 ; gain = 477.281
INFO: [Project 1-571] Translating synthesized netlist
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 750.770 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

INFO: [Common 17-83] Releasing license: Synthesis
15 Infos, 14 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:26 ; elapsed = 00:00:28 . Memory (MB): peak = 750.863 ; gain = 497.270
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 750.863 ; gain = 0.000
WARNING: [Constraints 18-5210] No constraints selected for write.
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
INFO: [Common 17-1381] The checkpoint 'C:/Users/iggyg/OneDrive/Documents/alchitry/DeleteMeErrorTest/work/vivado/DeleteMeErrorTest/DeleteMeErrorTest.runs/synth_1/au_top_0.dcp' has been generated.
INFO: [runtcl-4] Executing : report_utilization -file au_top_0_utilization_synth.rpt -pb au_top_0_utilization_synth.pb
INFO: [Common 17-206] Exiting Vivado at Fri Mar 22 13:08:32 2019...
[Fri Mar 22 13:08:37 2019] synth_1 finished
wait_on_run: Time (s): cpu = 00:00:00 ; elapsed = 00:00:40 . Memory (MB): peak = 262.074 ; gain = 0.000
# launch_runs impl_1 -to_step write_bitstream -jobs 8
[Fri Mar 22 13:08:38 2019] Launched impl_1...
Run output will be captured here: C:/Users/iggyg/OneDrive/Documents/alchitry/DeleteMeErrorTest/work/vivado/DeleteMeErrorTest/DeleteMeErrorTest.runs/impl_1/runme.log
# wait_on_run impl_1
[Fri Mar 22 13:08:38 2019] Waiting for impl_1 to finish...

*** Running vivado
   with args -log au_top_0.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source au_top_0.tcl -notrace


****** Vivado v2018.3 (64-bit)
 **** SW Build 2405991 on Thu Dec  6 23:38:27 MST 2018
 **** IP Build 2404404 on Fri Dec  7 01:43:56 MST 2018
   ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.

source au_top_0.tcl -notrace
Command: link_design -top au_top_0 -part xc7a35tftg256-1
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
INFO: [Project 1-479] Netlist was created with Vivado 2018.3
INFO: [Device 21-403] Loading part xc7a35tftg256-1
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [C:/Users/iggyg/OneDrive/Documents/alchitry/DeleteMeErrorTest/work/constraint/testclksig.xdc]
Finished Parsing XDC File [C:/Users/iggyg/OneDrive/Documents/alchitry/DeleteMeErrorTest/work/constraint/testclksig.xdc]
Parsing XDC File [C:/Program Files/Alchitry/Alchitry Labs/library/components/au.xdc]
Finished Parsing XDC File [C:/Program Files/Alchitry/Alchitry Labs/library/components/au.xdc]
Parsing XDC File [C:/Users/iggyg/OneDrive/Documents/alchitry/DeleteMeErrorTest/work/constraint/alchitry.xdc]
Finished Parsing XDC File [C:/Users/iggyg/OneDrive/Documents/alchitry/DeleteMeErrorTest/work/constraint/alchitry.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 570.566 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

5 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
link_design completed successfully
link_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 574.762 ; gain = 320.727
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
Running DRC as a precondition to command opt_design

Starting DRC Task
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.780 . Memory (MB): peak = 585.547 ; gain = 10.785

Starting Cache Timing Information Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Cache Timing Information Task | Checksum: 1cb8c7a91

Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1102.551 ; gain = 517.004

Starting Logic Optimization Task

Phase 1 Retarget
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 1 Retarget | Checksum: 1cb8c7a91

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 1198.867 ; gain = 0.000
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells

Phase 2 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 2 Constant propagation | Checksum: 1cb8c7a91

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.011 . Memory (MB): peak = 1198.867 ; gain = 0.000
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells

Phase 3 Sweep
Phase 3 Sweep | Checksum: 1cb8c7a91

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 1198.867 ; gain = 0.000
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells

Phase 4 BUFG optimization
Phase 4 BUFG optimization | Checksum: 1cb8c7a91

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.014 . Memory (MB): peak = 1198.867 ; gain = 0.000
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.

Phase 5 Shift Register Optimization
Phase 5 Shift Register Optimization | Checksum: 1cb8c7a91

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.033 . Memory (MB): peak = 1198.867 ; gain = 0.000
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells

Phase 6 Post Processing Netlist
Phase 6 Post Processing Netlist | Checksum: 1cb8c7a91

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.034 . Memory (MB): peak = 1198.867 ; gain = 0.000
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
Opt_design Change Summary
=========================


-------------------------------------------------------------------------------------------------------------------------
|  Phase                        |  #Cells created  |  #Cells Removed  |  #Constrained objects preventing optimizations  |
-------------------------------------------------------------------------------------------------------------------------
|  Retarget                     |               0  |               0  |                                              0  |
|  Constant propagation         |               0  |               0  |                                              0  |
|  Sweep                        |               0  |               0  |                                              0  |
|  BUFG optimization            |               0  |               0  |                                              0  |
|  Shift Register Optimization  |               0  |               0  |                                              0  |
|  Post Processing Netlist      |               0  |               0  |                                              0  |
-------------------------------------------------------------------------------------------------------------------------



Starting Connectivity Check Task

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1198.867 ; gain = 0.000
Ending Logic Optimization Task | Checksum: 1cb8c7a91

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.037 . Memory (MB): peak = 1198.867 ; gain = 0.000

Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
Ending Power Optimization Task | Checksum: 1cb8c7a91

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 1198.867 ; gain = 0.000

Starting Final Cleanup Task
Ending Final Cleanup Task | Checksum: 1cb8c7a91

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1198.867 ; gain = 0.000

Starting Netlist Obfuscation Task
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1198.867 ; gain = 0.000
Ending Netlist Obfuscation Task | Checksum: 1cb8c7a91

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1198.867 ; gain = 0.000
INFO: [Common 17-83] Releasing license: Implementation
21 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 1198.867 ; gain = 624.105
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1198.867 ; gain = 0.000
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.047 . Memory (MB): peak = 1198.867 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1198.867 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'C:/Users/iggyg/OneDrive/Documents/alchitry/DeleteMeErrorTest/work/vivado/DeleteMeErrorTest/DeleteMeErrorTest.runs/impl_1/au_top_0_opt.dcp' has been generated.
INFO: [runtcl-4] Executing : report_drc -file au_top_0_drc_opted.rpt -pb au_top_0_drc_opted.pb -rpx au_top_0_drc_opted.rpx
Command: report_drc -file au_top_0_drc_opted.rpt -pb au_top_0_drc_opted.pb -rpx au_top_0_drc_opted.rpx
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2018.3/data/ip'.
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/iggyg/OneDrive/Documents/alchitry/DeleteMeErrorTest/work/vivado/DeleteMeErrorTest/DeleteMeErrorTest.runs/impl_1/au_top_0_drc_opted.rpt.
report_drc completed successfully
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.

Starting Placer Task
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs

Phase 1 Placer Initialization

Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1198.867 ; gain = 0.000
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 191b49df5

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1198.867 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1198.867 ; gain = 0.000

Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 167a68e6a

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.743 . Memory (MB): peak = 1208.055 ; gain = 9.188

Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: 1ca081910

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.791 . Memory (MB): peak = 1215.703 ; gain = 16.836

Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: 1ca081910

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.794 . Memory (MB): peak = 1215.703 ; gain = 16.836
Phase 1 Placer Initialization | Checksum: 1ca081910

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.794 . Memory (MB): peak = 1215.703 ; gain = 16.836

Phase 2 Global Placement

Phase 2.1 Floorplanning
Phase 2.1 Floorplanning | Checksum: 2216dc132

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.845 . Memory (MB): peak = 1215.703 ; gain = 16.836

Phase 2.2 Physical Synthesis In Placer
INFO: [Physopt 32-65] No nets found for high-fanout optimization.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-670] No setup violation found.  DSP Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found.  Shift Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found.  BRAM Register Optimization was not performed.
INFO: [Physopt 32-949] No candidate nets found for HD net replication
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1215.703 ; gain = 0.000

Summary of Physical Synthesis Optimizations
============================================


----------------------------------------------------------------------------------------------------------------------------------------
|  Optimization                  |  Added Cells  |  Removed Cells  |  Optimized Cells/Nets  |  Dont Touch  |  Iterations  |  Elapsed   |
----------------------------------------------------------------------------------------------------------------------------------------
|  Very High Fanout              |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  DSP Register                  |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
|  Shift Register                |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
|  BRAM Register                 |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
|  HD Interface Net Replication  |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Total                         |            0  |              0  |                     0  |           0  |           2  |  00:00:00  |
----------------------------------------------------------------------------------------------------------------------------------------


Phase 2.2 Physical Synthesis In Placer | Checksum: 259f947a6

Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1215.703 ; gain = 16.836
Phase 2 Global Placement | Checksum: 239191fe5

Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1215.703 ; gain = 16.836

Phase 3 Detail Placement

Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: 239191fe5

Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1215.703 ; gain = 16.836

Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1821ab764

Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1215.703 ; gain = 16.836

Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 2119c19a6

Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1215.703 ; gain = 16.836

Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 19ec0be78

Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1215.703 ; gain = 16.836

Phase 3.5 Small Shape Detail Placement
Phase 3.5 Small Shape Detail Placement | Checksum: 190de752b

Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1215.703 ; gain = 16.836

Phase 3.6 Re-assign LUT pins
Phase 3.6 Re-assign LUT pins | Checksum: 190de752b

Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1215.703 ; gain = 16.836

Phase 3.7 Pipeline Register Optimization
Phase 3.7 Pipeline Register Optimization | Checksum: 206c9ea5d

Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1215.703 ; gain = 16.836
Phase 3 Detail Placement | Checksum: 206c9ea5d

Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1215.703 ; gain = 16.836

Phase 4 Post Placement Optimization and Clean-Up

Phase 4.1 Post Commit Optimization
INFO: [Timing 38-35] Done setting XDC timing constraints.

Phase 4.1.1 Post Placement Optimization
Post Placement Optimization Initialization | Checksum: 1b8d14fed

Phase 4.1.1.1 BUFG Insertion
INFO: [Place 46-46] BUFG insertion identified 0 candidate nets, 0 success, 0 bufg driver replicated, 0 skipped for placement/routing, 0 skipped for timing, 0 skipped for netlist change reason
Phase 4.1.1.1 BUFG Insertion | Checksum: 1b8d14fed

Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1215.703 ; gain = 16.836
INFO: [Place 30-746] Post Placement Timing Summary WNS=7.829. For the most accurate timing information please run report_timing.
Phase 4.1.1 Post Placement Optimization | Checksum: 1d698bc3c

Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1215.703 ; gain = 16.836
Phase 4.1 Post Commit Optimization | Checksum: 1d698bc3c

Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1215.703 ; gain = 16.836

Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: 1d698bc3c

Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1215.703 ; gain = 16.836

Phase 4.3 Placer Reporting
Phase 4.3 Placer Reporting | Checksum: 1d698bc3c

Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1215.703 ; gain = 16.836

Phase 4.4 Final Placement Cleanup
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1215.703 ; gain = 0.000
Phase 4.4 Final Placement Cleanup | Checksum: 1d698bc3c

Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1215.703 ; gain = 16.836
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1d698bc3c

Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1215.703 ; gain = 16.836
Ending Placer Task | Checksum: 17b4c51de

Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1215.703 ; gain = 16.836
INFO: [Common 17-83] Releasing license: Implementation
50 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1215.703 ; gain = 0.000
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.048 . Memory (MB): peak = 1215.883 ; gain = 0.180
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1221.902 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'C:/Users/iggyg/OneDrive/Documents/alchitry/DeleteMeErrorTest/work/vivado/DeleteMeErrorTest/DeleteMeErrorTest.runs/impl_1/au_top_0_placed.dcp' has been generated.
INFO: [runtcl-4] Executing : report_io -file au_top_0_io_placed.rpt
report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.081 . Memory (MB): peak = 1222.777 ; gain = 0.000
INFO: [runtcl-4] Executing : report_utilization -file au_top_0_utilization_placed.rpt -pb au_top_0_utilization_placed.pb
INFO: [runtcl-4] Executing : report_control_sets -verbose -file au_top_0_control_sets_placed.rpt
report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 1222.777 ; gain = 0.000
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
Running DRC as a precondition to command route_design
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.


Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
Checksum: PlaceDB: 9dcdb7b5 ConstDB: 0 ShapeSum: dd7e9a29 RouteDB: 0

Phase 1 Build RT Design
Phase 1 Build RT Design | Checksum: 14253932d

Time (s): cpu = 00:00:25 ; elapsed = 00:00:22 . Memory (MB): peak = 1344.742 ; gain = 121.965
Post Restoration Checksum: NetGraph: b628cf02 NumContArr: 8c2ac42b Constraints: 0 Timing: 0

Phase 2 Router Initialization

Phase 2.1 Create Timer
Phase 2.1 Create Timer | Checksum: 14253932d

Time (s): cpu = 00:00:25 ; elapsed = 00:00:22 . Memory (MB): peak = 1364.910 ; gain = 142.133

Phase 2.2 Fix Topology Constraints
Phase 2.2 Fix Topology Constraints | Checksum: 14253932d

Time (s): cpu = 00:00:25 ; elapsed = 00:00:22 . Memory (MB): peak = 1370.938 ; gain = 148.160

Phase 2.3 Pre Route Cleanup
Phase 2.3 Pre Route Cleanup | Checksum: 14253932d

Time (s): cpu = 00:00:25 ; elapsed = 00:00:22 . Memory (MB): peak = 1370.938 ; gain = 148.160
Number of Nodes with overlaps = 0

Phase 2.4 Update Timing
Phase 2.4 Update Timing | Checksum: 172e7aabf

Time (s): cpu = 00:00:25 ; elapsed = 00:00:23 . Memory (MB): peak = 1374.629 ; gain = 151.852
INFO: [Route 35-416] Intermediate Timing Summary | WNS=7.825  | TNS=0.000  | WHS=-0.210 | THS=-0.386 |

Phase 2 Router Initialization | Checksum: 16b1d28c7

Time (s): cpu = 00:00:25 ; elapsed = 00:00:23 . Memory (MB): peak = 1374.629 ; gain = 151.852

Phase 3 Initial Routing
Phase 3 Initial Routing | Checksum: 9754d64a

Time (s): cpu = 00:00:25 ; elapsed = 00:00:23 . Memory (MB): peak = 1375.586 ; gain = 152.809

Phase 4 Rip-up And Reroute

Phase 4.1 Global Iteration 0
Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=6.609  | TNS=0.000  | WHS=N/A    | THS=N/A    |

Phase 4.1 Global Iteration 0 | Checksum: 2205f6a67

Time (s): cpu = 00:00:25 ; elapsed = 00:00:23 . Memory (MB): peak = 1375.586 ; gain = 152.809
Phase 4 Rip-up And Reroute | Checksum: 2205f6a67

Time (s): cpu = 00:00:25 ; elapsed = 00:00:23 . Memory (MB): peak = 1375.586 ; gain = 152.809

Phase 5 Delay and Skew Optimization

Phase 5.1 Delay CleanUp
Phase 5.1 Delay CleanUp | Checksum: 2205f6a67

Time (s): cpu = 00:00:25 ; elapsed = 00:00:23 . Memory (MB): peak = 1375.586 ; gain = 152.809

Phase 5.2 Clock Skew Optimization
Phase 5.2 Clock Skew Optimization | Checksum: 2205f6a67

Time (s): cpu = 00:00:25 ; elapsed = 00:00:23 . Memory (MB): peak = 1375.586 ; gain = 152.809
Phase 5 Delay and Skew Optimization | Checksum: 2205f6a67

Time (s): cpu = 00:00:25 ; elapsed = 00:00:23 . Memory (MB): peak = 1375.586 ; gain = 152.809

Phase 6 Post Hold Fix

Phase 6.1 Hold Fix Iter

Phase 6.1.1 Update Timing
Phase 6.1.1 Update Timing | Checksum: 197148ac2

Time (s): cpu = 00:00:25 ; elapsed = 00:00:23 . Memory (MB): peak = 1375.586 ; gain = 152.809
INFO: [Route 35-416] Intermediate Timing Summary | WNS=6.609  | TNS=0.000  | WHS=0.226  | THS=0.000  |

Phase 6.1 Hold Fix Iter | Checksum: 1aac50cad

Time (s): cpu = 00:00:25 ; elapsed = 00:00:23 . Memory (MB): peak = 1375.586 ; gain = 152.809
Phase 6 Post Hold Fix | Checksum: 1aac50cad

Time (s): cpu = 00:00:25 ; elapsed = 00:00:23 . Memory (MB): peak = 1375.586 ; gain = 152.809

Phase 7 Route finalize

Router Utilization Summary
 Global Vertical Routing Utilization    = 0.00908874 %
 Global Horizontal Routing Utilization  = 0.00676731 %
 Routable Net Status*
 *Does not include unroutable nets such as driverless and loadless.
 Run report_route_status for detailed report.
 Number of Failed Nets               = 0
 Number of Unrouted Nets             = 0
 Number of Partially Routed Nets     = 0
 Number of Node Overlaps             = 0

Phase 7 Route finalize | Checksum: 17d0ee992

Time (s): cpu = 00:00:25 ; elapsed = 00:00:23 . Memory (MB): peak = 1375.586 ; gain = 152.809

Phase 8 Verifying routed nets

Verification completed successfully
Phase 8 Verifying routed nets | Checksum: 17d0ee992

Time (s): cpu = 00:00:25 ; elapsed = 00:00:23 . Memory (MB): peak = 1377.594 ; gain = 154.816

Phase 9 Depositing Routes
Phase 9 Depositing Routes | Checksum: 17d0ee992

Time (s): cpu = 00:00:25 ; elapsed = 00:00:23 . Memory (MB): peak = 1377.594 ; gain = 154.816

Phase 10 Post Router Timing
INFO: [Route 35-57] Estimated Timing Summary | WNS=6.609  | TNS=0.000  | WHS=0.226  | THS=0.000  |

INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
Phase 10 Post Router Timing | Checksum: 17d0ee992

Time (s): cpu = 00:00:25 ; elapsed = 00:00:23 . Memory (MB): peak = 1377.594 ; gain = 154.816
INFO: [Route 35-16] Router Completed Successfully

Time (s): cpu = 00:00:25 ; elapsed = 00:00:23 . Memory (MB): peak = 1377.594 ; gain = 154.816

Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
67 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:00:28 ; elapsed = 00:00:24 . Memory (MB): peak = 1377.594 ; gain = 154.816
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1377.594 ; gain = 0.000
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.054 . Memory (MB): peak = 1377.594 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1377.594 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'C:/Users/iggyg/OneDrive/Documents/alchitry/DeleteMeErrorTest/work/vivado/DeleteMeErrorTest/DeleteMeErrorTest.runs/impl_1/au_top_0_routed.dcp' has been generated.
INFO: [runtcl-4] Executing : report_drc -file au_top_0_drc_routed.rpt -pb au_top_0_drc_routed.pb -rpx au_top_0_drc_routed.rpx
Command: report_drc -file au_top_0_drc_routed.rpt -pb au_top_0_drc_routed.pb -rpx au_top_0_drc_routed.rpx
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/iggyg/OneDrive/Documents/alchitry/DeleteMeErrorTest/work/vivado/DeleteMeErrorTest/DeleteMeErrorTest.runs/impl_1/au_top_0_drc_routed.rpt.
report_drc completed successfully
INFO: [runtcl-4] Executing : report_methodology -file au_top_0_methodology_drc_routed.rpt -pb au_top_0_methodology_drc_routed.pb -rpx au_top_0_methodology_drc_routed.rpx
Command: report_methodology -file au_top_0_methodology_drc_routed.rpt -pb au_top_0_methodology_drc_routed.pb -rpx au_top_0_methodology_drc_routed.rpx
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [DRC 23-133] Running Methodology with 2 threads
INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/iggyg/OneDrive/Documents/alchitry/DeleteMeErrorTest/work/vivado/DeleteMeErrorTest/DeleteMeErrorTest.runs/impl_1/au_top_0_methodology_drc_routed.rpt.
report_methodology completed successfully
INFO: [runtcl-4] Executing : report_power -file au_top_0_power_routed.rpt -pb au_top_0_power_summary_routed.pb -rpx au_top_0_power_routed.rpx
Command: report_power -file au_top_0_power_routed.rpt -pb au_top_0_power_summary_routed.pb -rpx au_top_0_power_routed.rpx
INFO: [Timing 38-35] Done setting XDC timing constraints.
Running Vector-less Activity Propagation...

Finished Running Vector-less Activity Propagation
79 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
INFO: [runtcl-4] Executing : report_route_status -file au_top_0_route_status.rpt -pb au_top_0_route_status.pb
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file au_top_0_timing_summary_routed.rpt -pb au_top_0_timing_summary_routed.pb -rpx au_top_0_timing_summary_routed.rpx -warn_on_violation
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
INFO: [runtcl-4] Executing : report_incremental_reuse -file au_top_0_incremental_reuse_routed.rpt
INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
INFO: [runtcl-4] Executing : report_clock_utilization -file au_top_0_clock_utilization_routed.rpt
INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file au_top_0_bus_skew_routed.rpt -pb au_top_0_bus_skew_routed.pb -rpx au_top_0_bus_skew_routed.rpx
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
Command: write_bitstream -force au_top_0.bit -bin_file
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
Running DRC as a precondition to command write_bitstream
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [DRC 23-27] Running DRC with 2 threads
ERROR: [DRC NSTD-1] Unspecified I/O Standard: 1 out of 14 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: testClk.
ERROR: [DRC UCIO-1] Unconstrained Logical Port: 1 out of 14 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined.  To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run.  Problem ports: testClk.
INFO: [Vivado 12-3199] DRC finished with 2 Errors
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
ERROR: [Vivado 12-1345] Error(s) found during DRC. Bitgen not run.
INFO: [Common 17-83] Releasing license: Implementation
95 Infos, 0 Warnings, 0 Critical Warnings and 3 Errors encountered.
write_bitstream failed
ERROR: [Common 17-39] 'write_bitstream' failed due to earlier errors.

INFO: [Common 17-206] Exiting Vivado at Fri Mar 22 13:09:48 2019...
[Fri Mar 22 13:09:49 2019] impl_1 finished
wait_on_run: Time (s): cpu = 00:00:00 ; elapsed = 00:01:11 . Memory (MB): peak = 262.074 ; gain = 0.000
INFO: [Common 17-206] Exiting Vivado at Fri Mar 22 13:09:49 2019...

Bin file (C:\Users\iggyg\OneDrive\Documents\alchitry\DeleteMeErrorTest\work\vivado\DeleteMeErrorTest\DeleteMeErrorTest.runs\impl_1\au_top_0.bin) could not be found! The build probably failed.
EDIT: Since I realize that I haven't posted my constraint file yet, here it is as well:

Code:
clock testClk 50MHz;
pin testIn B45;



RE: Clock Signals - alchitry - 03-26-2019

You also need to specify the clocks location using the pin command. So something like this.
Code:
clock testClk 50MHz;
pin testClk B46;
pin testIn B45;



RE: Clock Signals - iggyglass - 03-29-2019

Apologies for the late reply as I have been on vacation. I have edited my constraints file so it now reads
Code:
clock testClk 50MHz;
pin testClk B46;
pin testIn B45;
as you previously suggested. Despite this, the build still fails. Here is the build output:
Code:
****** Vivado v2018.3 (64-bit)
 **** SW Build 2405991 on Thu Dec  6 23:38:27 MST 2018
 **** IP Build 2404404 on Fri Dec  7 01:43:56 MST 2018
   ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.

source {C:\Users\iggyg\OneDrive\Documents\alchitry\DeleteMeErrorTest\work\project.tcl}
# set projDir "C:/Users/iggyg/OneDrive/Documents/alchitry/DeleteMeErrorTest/work/vivado"
# set projName "DeleteMeErrorTest"
# set topName top
# set device xc7a35tftg256-1
# if {[file exists "$projDir/$projName"]} { file delete -force "$projDir/$projName" }
# create_project $projName "$projDir/$projName" -part $device
INFO: [ProjectBase 1-489] The host OS only allows 260 characters in a normal path. The project is stored in a path with more than 80 characters. If you experience issues with IP, Block Designs, or files not being found, please consider moving the project to a location with a shorter path. Alternately consider using the OS subst command to map part of the path to a drive letter.
Current project path is 'C:/Users/iggyg/OneDrive/Documents/alchitry/DeleteMeErrorTest/work/vivado/DeleteMeErrorTest'
# set_property design_mode RTL [get_filesets sources_1]
# set verilogSources [list "C:/Users/iggyg/OneDrive/Documents/alchitry/DeleteMeErrorTest/work/verilog/au_top_0.v" "C:/Users/iggyg/OneDrive/Documents/alchitry/DeleteMeErrorTest/work/verilog/reset_conditioner_1.v"]
# import_files -fileset [get_filesets sources_1] -force -norecurse $verilogSources
# set xdcSources [list "C:/Users/iggyg/OneDrive/Documents/alchitry/DeleteMeErrorTest/work/constraint/testclksig.xdc" "C:/Program\ Files/Alchitry/Alchitry\ Labs/library/components/au.xdc" "C:/Users/iggyg/OneDrive/Documents/alchitry/DeleteMeErrorTest/work/constraint/alchitry.xdc" ]
# read_xdc $xdcSources
# set_property STEPS.WRITE_BITSTREAM.ARGS.BIN_FILE true [get_runs impl_1]
# update_compile_order -fileset sources_1
# launch_runs -runs synth_1 -jobs 8
[Thu Mar 28 18:48:50 2019] Launched synth_1...
Run output will be captured here: C:/Users/iggyg/OneDrive/Documents/alchitry/DeleteMeErrorTest/work/vivado/DeleteMeErrorTest/DeleteMeErrorTest.runs/synth_1/runme.log
# wait_on_run synth_1
[Thu Mar 28 18:48:50 2019] Waiting for synth_1 to finish...

*** Running vivado
   with args -log au_top_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source au_top_0.tcl


****** Vivado v2018.3 (64-bit)
 **** SW Build 2405991 on Thu Dec  6 23:38:27 MST 2018
 **** IP Build 2404404 on Fri Dec  7 01:43:56 MST 2018
   ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.

source au_top_0.tcl -notrace
Command: synth_design -top au_top_0 -part xc7a35tftg256-1
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35t'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t'
INFO: Launching helper process for spawning children vivado processes
INFO: Helper process launched with PID 3724
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 361.824 ; gain = 100.813
---------------------------------------------------------------------------------
INFO: [Synth 8-6157] synthesizing module 'au_top_0' [C:/Users/iggyg/OneDrive/Documents/alchitry/DeleteMeErrorTest/work/vivado/DeleteMeErrorTest/DeleteMeErrorTest.srcs/sources_1/imports/verilog/au_top_0.v:7]
INFO: [Synth 8-6157] synthesizing module 'reset_conditioner_1' [C:/Users/iggyg/OneDrive/Documents/alchitry/DeleteMeErrorTest/work/vivado/DeleteMeErrorTest/DeleteMeErrorTest.srcs/sources_1/imports/verilog/reset_conditioner_1.v:11]
    Parameter STAGES bound to: 3'b100
INFO: [Synth 8-6155] done synthesizing module 'reset_conditioner_1' (1#1) [C:/Users/iggyg/OneDrive/Documents/alchitry/DeleteMeErrorTest/work/vivado/DeleteMeErrorTest/DeleteMeErrorTest.srcs/sources_1/imports/verilog/reset_conditioner_1.v:11]
INFO: [Synth 8-6155] done synthesizing module 'au_top_0' (2#1) [C:/Users/iggyg/OneDrive/Documents/alchitry/DeleteMeErrorTest/work/vivado/DeleteMeErrorTest/DeleteMeErrorTest.srcs/sources_1/imports/verilog/au_top_0.v:7]
WARNING: [Synth 8-3917] design au_top_0 has port led[7] driven by constant 0
WARNING: [Synth 8-3917] design au_top_0 has port led[6] driven by constant 0
WARNING: [Synth 8-3917] design au_top_0 has port led[5] driven by constant 0
WARNING: [Synth 8-3917] design au_top_0 has port led[4] driven by constant 0
WARNING: [Synth 8-3917] design au_top_0 has port led[3] driven by constant 0
WARNING: [Synth 8-3917] design au_top_0 has port led[2] driven by constant 0
WARNING: [Synth 8-3917] design au_top_0 has port led[1] driven by constant 0
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 417.434 ; gain = 156.422
---------------------------------------------------------------------------------

Report Check Netlist:
+------+------------------+-------+---------+-------+------------------+
|      |Item              |Errors |Warnings |Status |Description       |
+------+------------------+-------+---------+-------+------------------+
|1     |multi_driven_nets |      0|        0|Passed |Multi driven nets |
+------+------------------+-------+---------+-------+------------------+
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 417.434 ; gain = 156.422
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 417.434 ; gain = 156.422
---------------------------------------------------------------------------------
INFO: [Device 21-403] Loading part xc7a35tftg256-1
INFO: [Project 1-570] Preparing netlist for logic optimization

Processing XDC Constraints
Initializing timing engine
Parsing XDC File [C:/Users/iggyg/OneDrive/Documents/alchitry/DeleteMeErrorTest/work/constraint/testclksig.xdc]
Finished Parsing XDC File [C:/Users/iggyg/OneDrive/Documents/alchitry/DeleteMeErrorTest/work/constraint/testclksig.xdc]
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [C:/Users/iggyg/OneDrive/Documents/alchitry/DeleteMeErrorTest/work/constraint/testclksig.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/au_top_0_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/au_top_0_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Parsing XDC File [C:/Program Files/Alchitry/Alchitry Labs/library/components/au.xdc]
Finished Parsing XDC File [C:/Program Files/Alchitry/Alchitry Labs/library/components/au.xdc]
Parsing XDC File [C:/Users/iggyg/OneDrive/Documents/alchitry/DeleteMeErrorTest/work/constraint/alchitry.xdc]
Finished Parsing XDC File [C:/Users/iggyg/OneDrive/Documents/alchitry/DeleteMeErrorTest/work/constraint/alchitry.xdc]
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [C:/Users/iggyg/OneDrive/Documents/alchitry/DeleteMeErrorTest/work/constraint/alchitry.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/au_top_0_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/au_top_0_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 691.098 ; gain = 0.000
Completed Processing XDC Constraints

Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 691.098 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 691.098 ; gain = 0.000
Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 691.098 ; gain = 0.000
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 691.098 ; gain = 430.086
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7a35tftg256-1
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 691.098 ; gain = 430.086
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 691.098 ; gain = 430.086
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 691.098 ; gain = 430.086
---------------------------------------------------------------------------------

Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start RTL Component Statistics
---------------------------------------------------------------------------------
Detailed RTL Component Info :
+---Registers :
                    4 Bit    Registers := 1    
                    1 Bit    Registers := 1    
---------------------------------------------------------------------------------
Finished RTL Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Hierarchical Component Statistics
---------------------------------------------------------------------------------
Hierarchical RTL Component report
Module au_top_0
Detailed RTL Component Info :
+---Registers :
                    1 Bit    Registers := 1    
Module reset_conditioner_1
Detailed RTL Component Info :
+---Registers :
                    4 Bit    Registers := 1    
---------------------------------------------------------------------------------
Finished RTL Hierarchical Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 90 (col length:60)
BRAMs: 100 (col length: RAMB18 60 RAMB36 30)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
Warning: Parallel synthesis criteria is not met
WARNING: [Synth 8-3917] design au_top_0 has port led[7] driven by constant 0
WARNING: [Synth 8-3917] design au_top_0 has port led[6] driven by constant 0
WARNING: [Synth 8-3917] design au_top_0 has port led[5] driven by constant 0
WARNING: [Synth 8-3917] design au_top_0 has port led[4] driven by constant 0
WARNING: [Synth 8-3917] design au_top_0 has port led[3] driven by constant 0
WARNING: [Synth 8-3917] design au_top_0 has port led[2] driven by constant 0
WARNING: [Synth 8-3917] design au_top_0 has port led[1] driven by constant 0
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 691.098 ; gain = 430.086
---------------------------------------------------------------------------------

Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 728.930 ; gain = 467.918
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 728.930 ; gain = 467.918
---------------------------------------------------------------------------------

Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 738.457 ; gain = 477.445
---------------------------------------------------------------------------------

Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 738.457 ; gain = 477.445
---------------------------------------------------------------------------------

Report Check Netlist:
+------+------------------+-------+---------+-------+------------------+
|      |Item              |Errors |Warnings |Status |Description       |
+------+------------------+-------+---------+-------+------------------+
|1     |multi_driven_nets |      0|        0|Passed |Multi driven nets |
+------+------------------+-------+---------+-------+------------------+
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 738.457 ; gain = 477.445
---------------------------------------------------------------------------------

Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 738.457 ; gain = 477.445
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 738.457 ; gain = 477.445
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 738.457 ; gain = 477.445
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 738.457 ; gain = 477.445
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------

Report BlackBoxes:
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+

Report Cell Usage:
+------+-----+------+
|      |Cell |Count |
+------+-----+------+
|1     |BUFG |     2|
|2     |LUT1 |     1|
|3     |FDRE |     1|
|4     |FDSE |     4|
|5     |IBUF |     5|
|6     |OBUF |     9|
+------+-----+------+

Report Instance Areas:
+------+-------------+--------------------+------+
|      |Instance     |Module              |Cells |
+------+-------------+--------------------+------+
|1     |top          |                    |    22|
|2     |  reset_cond |reset_conditioner_1 |     5|
+------+-------------+--------------------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 738.457 ; gain = 477.445
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 7 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:12 ; elapsed = 00:00:15 . Memory (MB): peak = 738.457 ; gain = 203.781
Synthesis Optimization Complete : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 738.457 ; gain = 477.445
INFO: [Project 1-571] Translating synthesized netlist
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 748.523 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

INFO: [Common 17-83] Releasing license: Synthesis
15 Infos, 14 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 748.523 ; gain = 495.250
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 748.523 ; gain = 0.000
WARNING: [Constraints 18-5210] No constraints selected for write.
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
INFO: [Common 17-1381] The checkpoint 'C:/Users/iggyg/OneDrive/Documents/alchitry/DeleteMeErrorTest/work/vivado/DeleteMeErrorTest/DeleteMeErrorTest.runs/synth_1/au_top_0.dcp' has been generated.
INFO: [runtcl-4] Executing : report_utilization -file au_top_0_utilization_synth.rpt -pb au_top_0_utilization_synth.pb
INFO: [Common 17-206] Exiting Vivado at Thu Mar 28 18:49:17 2019...
[Thu Mar 28 18:49:20 2019] synth_1 finished
wait_on_run: Time (s): cpu = 00:00:00 ; elapsed = 00:00:30 . Memory (MB): peak = 261.520 ; gain = 0.000
# launch_runs impl_1 -to_step write_bitstream -jobs 8
[Thu Mar 28 18:49:20 2019] Launched impl_1...
Run output will be captured here: C:/Users/iggyg/OneDrive/Documents/alchitry/DeleteMeErrorTest/work/vivado/DeleteMeErrorTest/DeleteMeErrorTest.runs/impl_1/runme.log
# wait_on_run impl_1
[Thu Mar 28 18:49:20 2019] Waiting for impl_1 to finish...

*** Running vivado
   with args -log au_top_0.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source au_top_0.tcl -notrace


****** Vivado v2018.3 (64-bit)
 **** SW Build 2405991 on Thu Dec  6 23:38:27 MST 2018
 **** IP Build 2404404 on Fri Dec  7 01:43:56 MST 2018
   ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.

source au_top_0.tcl -notrace
Command: link_design -top au_top_0 -part xc7a35tftg256-1
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
INFO: [Project 1-479] Netlist was created with Vivado 2018.3
INFO: [Device 21-403] Loading part xc7a35tftg256-1
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [C:/Users/iggyg/OneDrive/Documents/alchitry/DeleteMeErrorTest/work/constraint/testclksig.xdc]
Finished Parsing XDC File [C:/Users/iggyg/OneDrive/Documents/alchitry/DeleteMeErrorTest/work/constraint/testclksig.xdc]
Parsing XDC File [C:/Program Files/Alchitry/Alchitry Labs/library/components/au.xdc]
Finished Parsing XDC File [C:/Program Files/Alchitry/Alchitry Labs/library/components/au.xdc]
Parsing XDC File [C:/Users/iggyg/OneDrive/Documents/alchitry/DeleteMeErrorTest/work/constraint/alchitry.xdc]
Finished Parsing XDC File [C:/Users/iggyg/OneDrive/Documents/alchitry/DeleteMeErrorTest/work/constraint/alchitry.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 571.547 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

5 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
link_design completed successfully
link_design: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 575.559 ; gain = 322.004
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
Running DRC as a precondition to command opt_design

Starting DRC Task
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.594 . Memory (MB): peak = 584.090 ; gain = 8.531

Starting Cache Timing Information Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Cache Timing Information Task | Checksum: 17ab8fc53

Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1102.477 ; gain = 518.387

Starting Logic Optimization Task

Phase 1 Retarget
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 1 Retarget | Checksum: 17ab8fc53

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 1198.035 ; gain = 0.000
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells

Phase 2 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 2 Constant propagation | Checksum: 17ab8fc53

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 1198.035 ; gain = 0.000
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells

Phase 3 Sweep
Phase 3 Sweep | Checksum: 17ab8fc53

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.011 . Memory (MB): peak = 1198.035 ; gain = 0.000
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells

Phase 4 BUFG optimization
Phase 4 BUFG optimization | Checksum: 17ab8fc53

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.012 . Memory (MB): peak = 1198.035 ; gain = 0.000
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.

Phase 5 Shift Register Optimization
Phase 5 Shift Register Optimization | Checksum: 17ab8fc53

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.024 . Memory (MB): peak = 1198.035 ; gain = 0.000
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells

Phase 6 Post Processing Netlist
Phase 6 Post Processing Netlist | Checksum: 17ab8fc53

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.026 . Memory (MB): peak = 1198.035 ; gain = 0.000
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
Opt_design Change Summary
=========================


-------------------------------------------------------------------------------------------------------------------------
|  Phase                        |  #Cells created  |  #Cells Removed  |  #Constrained objects preventing optimizations  |
-------------------------------------------------------------------------------------------------------------------------
|  Retarget                     |               0  |               0  |                                              0  |
|  Constant propagation         |               0  |               0  |                                              0  |
|  Sweep                        |               0  |               0  |                                              0  |
|  BUFG optimization            |               0  |               0  |                                              0  |
|  Shift Register Optimization  |               0  |               0  |                                              0  |
|  Post Processing Netlist      |               0  |               0  |                                              0  |
-------------------------------------------------------------------------------------------------------------------------



Starting Connectivity Check Task

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1198.035 ; gain = 0.000
Ending Logic Optimization Task | Checksum: 17ab8fc53

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.028 . Memory (MB): peak = 1198.035 ; gain = 0.000

Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
Ending Power Optimization Task | Checksum: 17ab8fc53

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 1198.035 ; gain = 0.000

Starting Final Cleanup Task
Ending Final Cleanup Task | Checksum: 17ab8fc53

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1198.035 ; gain = 0.000

Starting Netlist Obfuscation Task
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1198.035 ; gain = 0.000
Ending Netlist Obfuscation Task | Checksum: 17ab8fc53

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1198.035 ; gain = 0.000
INFO: [Common 17-83] Releasing license: Implementation
21 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1198.035 ; gain = 622.477
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1198.035 ; gain = 0.000
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.037 . Memory (MB): peak = 1198.035 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1198.035 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'C:/Users/iggyg/OneDrive/Documents/alchitry/DeleteMeErrorTest/work/vivado/DeleteMeErrorTest/DeleteMeErrorTest.runs/impl_1/au_top_0_opt.dcp' has been generated.
INFO: [runtcl-4] Executing : report_drc -file au_top_0_drc_opted.rpt -pb au_top_0_drc_opted.pb -rpx au_top_0_drc_opted.rpx
Command: report_drc -file au_top_0_drc_opted.rpt -pb au_top_0_drc_opted.pb -rpx au_top_0_drc_opted.rpx
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2018.3/data/ip'.
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/iggyg/OneDrive/Documents/alchitry/DeleteMeErrorTest/work/vivado/DeleteMeErrorTest/DeleteMeErrorTest.runs/impl_1/au_top_0_drc_opted.rpt.
report_drc completed successfully
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.

Starting Placer Task
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs

Phase 1 Placer Initialization

Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1198.035 ; gain = 0.000
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 140e11fb7

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1198.035 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1198.035 ; gain = 0.000

Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
INFO: [Timing 38-35] Done setting XDC timing constraints.
ERROR: [Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
    < set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets testClk_IBUF] >

    testClk_IBUF_inst (IBUF.O) is locked to IOB_X1Y85
    testClk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y31
Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two.  There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing.  This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin.
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 140e11fb7

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.595 . Memory (MB): peak = 1204.262 ; gain = 6.227
Phase 1 Placer Initialization | Checksum: 140e11fb7

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.597 . Memory (MB): peak = 1204.262 ; gain = 6.227
ERROR: [Place 30-99] Placer failed with error: 'IO Clock Placer failed'
Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure.
Ending Placer Task | Checksum: 140e11fb7

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.601 . Memory (MB): peak = 1204.262 ; gain = 6.227
INFO: [Common 17-83] Releasing license: Implementation
39 Infos, 0 Warnings, 0 Critical Warnings and 3 Errors encountered.
place_design failed
ERROR: [Common 17-69] Command failed: Placer could not place all instances
INFO: [Common 17-206] Exiting Vivado at Thu Mar 28 18:49:51 2019...
[Thu Mar 28 18:49:56 2019] impl_1 finished
wait_on_run: Time (s): cpu = 00:00:00 ; elapsed = 00:00:35 . Memory (MB): peak = 261.520 ; gain = 0.000
INFO: [Common 17-206] Exiting Vivado at Thu Mar 28 18:49:56 2019...

Bin file (C:\Users\iggyg\OneDrive\Documents\alchitry\DeleteMeErrorTest\work\vivado\DeleteMeErrorTest\DeleteMeErrorTest.runs\impl_1\au_top_0.bin) could not be found! The build probably failed.



RE: Clock Signals - iggyglass - 04-04-2019

Update: In case it was a bug, I just got around to updating to the newest version (1.0.6), and the build still fails. If you would like to see the new build output, let me know.


RE: Clock Signals - prebys - 04-09-2019

This isn't a bug, it's a feature. Xilinx doesn't like you using anything but dedicated clock lines for clocks and will issue a fatal error if you do. If you look through your log file, it tells you how to reduce this to a warning:

ERROR: [Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets testClk_IBUF] >

Just add this to your .xdc file and it should build, although you appear to have a second ERROR due to an undefined pin that has to be fixed as well.