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  Working loader for MacOS!
Posted by: prebys - 11-01-2020, 10:37 PM - Forum: Tips and Tricks - Replies (2)

We're going to be doing labs with these boards remotely next quarter, we've arranged for remote Windows systems to do the compilation, but half the students have Macs, so I needed a Mac version of the binary loader.  

I was able to pretty easily port the standalone (officially deprecated) command line alchitry-loader for MacOS by doing the following...

From here: https://www.ftdichip.com/Drivers/D2XX.htm
- Download the driver library for 10.4 and later
- Also download and install the "D2XX Helper Tool" (this prevents MacOS from overriding the drivers)
- Follow the instructional video (if you have the helper tool, you don't have to do the "kextunload" step)

Then do 
>git clone https://github.com/alchitry/alchitry-loader
>cd alchitry-loader/src
>c++ -o Alchitry_Loader *.cpp -lftd2xx -lpthread

This will generate a LOT of warnings (>70), but the resulting executable seems to run correctly. 

To test it, do
> ./Alchitry_Loader -l
and it should find the board and return
  0: Alchitry Au
  1: Unknown
Found Au as device 0.

To do a volatile load of a configuration, do
> ./Alchitry_Loader -r (project).bin  

If you want to erase or program the flash, you also need a "bridge" .bin file. You can find "au_loader.bin" and "cu_loader.bin" in this archive:

You then erase the flash with
> ./Alchitry_Loader -p au_loader.bin -e

and program it with
> ./Alchitry_Loader -p au_loader.bin -f project.bin

To date this has only been tested with an Alchitry Au under MacOS Catalina

  Flash Memory Mojo V3
Posted by: tistructor - 10-15-2020, 11:55 AM - Forum: General Questions - Replies (2)

I am building my own mojo V3 card, is it possible to use a SST25VF040B-50 (50Mhz) flash memory instead of the default 80Mhz one?
Thank you

  Au DDR tutorial gives "Critical Warning" on build
Posted by: Rory - 10-09-2020, 12:29 PM - Forum: General Questions - Replies (1)

I was duplicating the tutorial on how to use the DDR memory on the Au, but I get a Critical Warning upon building. 
The design runs ok, but the "Critical" part of the warning worries me a bit.

I think the problems start right at the start when I add the Memory Controller. It complains about not finding an .xci file:

[Image: img1.png]
Compare this to exactly the same stage in the tutorial:
[Image: img2.png]

It makes the same complaint after I add the clock wizard core (in fact it seems to say this after generating any cores).
When I add in all the code (exactly duplicating the tutorial), it successfully builds, but gives me the critical warning:

Parsing XDC File [C:/NarwhalDevices/FPGA_projects/DDR_example/work/constraint/alchitry.xdc]
CRITICAL WARNING: [Constraints 18-1056] Clock 'clk_0' completely overrides clock 'clk'.

Should I just ignore the warning, or is it a sign that there is something wrong, and it will come back to bite me?


Note: I'm using Windows 10, Alchitry Labs 1.2.1, and Vivado 2020.1
(see attachment for full output)

Attached Files
.txt   DDR tutorial Critical Warning.txt (Size: 84.02 KB / Downloads: 1)

  Alchitry Hd, Mo, Ft
Posted by: LMN128 - 10-05-2020, 04:20 PM - Forum: General Questions - Replies (1)

what is a progress of these modules production, please?[Image: aBCWwUFnSAqZNQKP9]

Attached Files
.jpg   EBOm1leXYAAq4Fy.jpg (Size: 497.25 KB / Downloads: 14)

  GTP / PCIe
Posted by: spinamathing - 10-01-2020, 05:37 PM - Forum: General Questions - Replies (1)

I was extremely excited when I found the Alchitry Au because I wanted to use the Artix 7's GTPs (to play with PCIe, amongst other things) but then when I dug into it I realized it's the FTG256 package that doesn't include the 4 GTPs Sad

Any chance youall will design / release an even fancier board that uses the CSG325 package instead so that we can use the GTPs and even do PCIe 2.0 4x lanes (with an adapter board)?  I'm assuming the FTG256 was selected due to the 1.0mm ball pitch instead of 0.8 and being slightly cheaper?

  Verilog example for Serial data transfer on Au
Posted by: anirbanbits - 09-26-2020, 10:17 PM - Forum: General Questions - Replies (1)

Hi, could you please share any examples on how to perform serial communication using Verilog on the Alchitry Au? The examples I saw in the tutorials section for serial comms were all for the Mojo board. 

What I have tried:
I see that in the top level module there are two ports: usb_rx(input) and usb_tx(output). I defined a register to hold an 8 bit data, assigned the usb_tx output port to this register. Then in the always block I updated the register but couldn't see any data show up on the serial port monitor. I feel like I am missing modules/IP that will make this work because nowhere do I see the ability to set baud rate or flow control in the default setup.

  IO element Constraints Broken in Vivado
Posted by: evander12345 - 09-20-2020, 10:00 PM - Forum: General Questions - Replies (1)

Hi everyone. New user to the forum as well as FPGAs. I'm hoping someone can help me solve this issue before I tear my hair out... and forgive me if this is an obvious issue, as this is my first time working with an FPGA.

So the issue that I'm having is that Vivado doesn't seem to want to synthesize my design after I tried to ad the IO element constraints to my project. I came across this thread here for generating an XDC constraint for the IO element "shield", but Vivado seems to not like this file at all. I keep getting the error "[Common 17-55] 'set_property' expects at least one object" for nearly every single line (lines 7+), and "[Common 17-69] Command failed: Site cannot be assigned to more than one port" for the lines 1,3,5.

I've attached my au.top and io.xdc for reference. Thanks for helping a n00b out.

Attached Files
.txt   io.txt (Size: 8.63 KB / Downloads: 5)
.txt   au_top.txt (Size: 813 bytes / Downloads: 2)

  Question Shield Mojo to Alchitry
Posted by: tistructor - 09-10-2020, 12:44 PM - Forum: General Questions - Replies (4)

I'm designing a circuit to make sure that the new Architry board shields can be mounted on Mojo V3.
Is it necessary that the wires from the mojo connectors to the new smd connectors have the same length?
From the photo of alchity Au the wires of equal length are the ones that go to the dram onboard but the ones that go to the connectors do not seem to me to be identical in length. Is that so?
In this last case it is not necessary that in the design of the pcb you implement the wires of equal length.

The attached file shows the board with 2 connectors with wires of identical length. But to make all 4 connectors the thing is quite complicated. It can be done but I have to waste some time.

I hope I have explained


Smile Constraints files
Posted by: TechPaula - 09-07-2020, 11:37 AM - Forum: General Questions - Replies (1)


  I've begun playing with my AU board in earnest now and I've found one constraints file for the LEDs and switch on board, but I'm wondering where I can get the others?
  for example constraints files for the IO board and also that which includes the DDR memory pins?

  Does anyone have a link they could share with me please?

Many thanks

  Greeter Tutorial on Au board
Posted by: rlovelacecap@hotmail.com - 09-07-2020, 01:17 AM - Forum: General Questions - Replies (1)

I've installed the Alchitry Labs software and successfully run many of the tutorial programs.
For the Greeter program, the guidance is to open up the Serial Port Monitor under Tools.

As soon as I try this, the Alchitry Labs software shuts down without any messages.

I'm running on a Win10/64 box, with the 1.2.0 development software.

Is there something I could have missed?

Any help would be greatly appreciated.