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Alchitry Board to Board C...
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CU board wont program
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Au can't work
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Can't get the Cu to work....
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  Au + Board IP's
Posted by: howdyrichard - 01-16-2022, 03:58 PM - Forum: General Questions - Replies (2)

First, I'm trying to add uarts to serial_port_echo and Alichity Labs doesn't like it.  I was able to make the additional pin assignments in Vivado and it worked.  Is there a way to run these tutorials in Vivado so I can add to the simulation without errors.  For example, when I added uart pins, described them in alchitry.acf, it left 'nulls' in place of the pin assignments in Vivado.  After filling them in, Vivado would create a usable bit stream but then I can't modify au_top_plus anymore. 

I do not see this board in Xilinx store so I can not get IP's created for it like you can other evaluation boards.  Is there a way to construct them with existing files in Alchitry Labs or am I wasting my time?  I need 3 extra rs-232 ports combined with DDR to make my project work and I am getting frustrated with trying to use Lucid outside of the demo tutorials.

Any comments would be appreciated.

Attached Files
.xdc   alchitry.xdc (Size: 1.92 KB / Downloads: 3)
.txt   alchitryacf.txt (Size: 375 bytes / Downloads: 3)

  FPGA configuration in SPI slave mode
Posted by: output - 01-15-2022, 01:52 PM - Forum: General Questions - Replies (1)

Before starting to dig in the schematics:  the AU and AU+ FPGA can be configured via USB.
How to handle this without USB ? Are the pins (and maybe mode selection pins) available to perform FPGA configuration in SPI slave mode (e.g. from a microcontroller)

Unless I am overlooking something, it seems there is no document explaining some basic functionality of the modules and by reverse engineering the schematic it's easy to overlook something.

  MicroBlaze & Au Plus
Posted by: howdyrichard - 01-09-2022, 09:56 PM - Forum: General Questions - Replies (1)

Can the MicroBlaze computer be accessed with Vivado/Vitis?

  AU Plus UART Capability
Posted by: howdyrichard - 12-30-2021, 02:54 PM - Forum: General Questions - Replies (2)

How many uarts can I setup with AU+? I'm hoping at least 4 to use for low speed (9600 BAUD) async sensors.

  ADC and HDMI clock synchornization
Posted by: cerkit - 12-27-2021, 02:21 PM - Forum: General Questions - No Replies


I am making a simple video synthesizer using the HDMI shield (on the Mojo). I have successfully generated my signal with the HDMI shield, but now I'd like to change the red/green/blue amount based on the input from the ADC. The ADC tutorial uses a PWM to control the LEDs based on the input from the ADC, but I'm just trying to get an 8 bit value out of it.

Also, it seems that since the ADC and the HDMI processing are on different clock domains, the signals from the ADC will not correctly "register" with the HDMI domain.

I tried setting the clock of the ADC to the clock that's provided by the HDMI Encoder component, but I get an error during synthesis.

Can anyone point me in the general direction of how to convert the input of the ADC into a simple 8 bit value between 0-254 that I can then use to set the value of the hdmi.red,.green, and .blue values?

Thanks in advance.

  HDMI Error - tmds_encoder.luc bug?
Posted by: cerkit - 12-26-2021, 03:30 AM - Forum: General Questions - Replies (1)


I am working through the HDMI shield demo and I've followed the instructions. However, I receive an error with the included tmds_encoder.luc file.

data9[i] = xor_flag ? data9[i-1] ~^ din.q[i] : data9[i-1] ^ din.q[i];

This code causes the following error:

Quote:Errors in file /home/michael/Alchitry/HDMI/HelloHDMI/HelloHDMI/source/tmds_encoder.luc:
    Line 48, Column 64 : missing '=' at '^'
    Line 48, Column 39 : missing ':' at '~'
    Line 48, Column 51 : mismatched input ':' expecting {'[', ']', '<', '.', '>', '+', '-', 'x{', '*', '/', '>>', '<<', '<<<', '>>>', '|', '&', '^', '==', '!=', '>=', '<=', '||', '&&', '?'}

I was able to get it working by making an editable copy of the file and switching the ~ and ^ operators on the true branch of the ternary operator like so:

data9[i] = xor_flag ? data9[i-1] ^ ~ din.q[i] : data9[i-1] ^ din.q[i];

Since I really don't know what a tmds encoder is actually supposed to do, the only way I've been able to debug my change is to place the design on my mojo and plug it into my monitor. It seems to be working, but I want to make sure I fixed the bug correctly and didn't introduce a bigger problem.

Thanks for your time.

  Serial Port Monitor is not Windows compatible
Posted by: tonyvr@sonic.net - 12-24-2021, 05:46 PM - Forum: General Questions - No Replies

I have enjoyed exploring the tutorials. I noticed that the built-in Serial Port Monitor is not Windows compatible, however, as it is missing a setting to use CR+LF for newlines. I have had to use Tera Term instead.

  Cannot Build Cu Hello World with IceStorm
Posted by: applekor - 12-17-2021, 12:17 AM - Forum: General Questions - No Replies

Has anyone on here been successful at building for Cu using IceStorm?  I built my toolchain by installing apio and following the instructions on FPGAWars' GitHub.  What is the ".sdc constraints" error about, and is it failing to build because I am specifying nextpnr instead of arachne-pnr and Alchitry Labs doesn't like it?  If that is the case, can Alchitry Labs be updated to use nextpnr, since arachne-pnr is deprecated?

Attached Files
.png   Alchitry Cu Build.png (Size: 45.5 KB / Downloads: 3)

  Connecting multiple FPGAs?
Posted by: stefanwebb - 12-14-2021, 08:43 PM - Forum: General Questions - Replies (2)

Hi There, I'm new to FPGAs and wanted to ask what may be a naive question:

Is it possible to connect multiple Alchitry Au boards via the IO pins? I.e. can you connect the output pins from a first board to input pins in a second and use the digital signal generated from the first board to drive the second one?

I am interested in combining several FPGAs to build more complex logic and scale up my prototypes

  Vivado prefered language?
Posted by: Jeroen - 12-08-2021, 05:58 PM - Forum: General Questions - Replies (1)

Hi all, 

I'm new to FPGA's but eager to learn the ins and outs of the Xilinx Vivado design suite for the Alchitry AU FPGA Development Board (realization of 3 custom-made shields as use-cases for a project at work). 

I'm here to seek advice what would be the best language to learn as base knowledge. I have experience in php, java, python and linux, but programming a fpga is a little different I understood Wink ?

For a good foundation is VHDL, or Verilog the best route to take as a language course to follow (next to the examples on this website) or is another language like C a better choice for me?

I work/learn best in a real (live) classroom setting, with an actual teacher, homework assignments and motivated colleague students, instead of an online course. Problem with VHDL or Verilog is that these languages are not very common, at least not in the Netherlands where I live. So to follow such a cource I can imagine an online course will be the solution.

If VHDL or Verilog is the route some of you took?? What course (url) would you advice to take? Udemy has a lot to offer, but what content is good?? I still prefer an actual real company to supply the course even if it cost lots more (if the quality is good). In the tutorial for the Alchitry boards I saw yet another language: Lucid. Is this the route to take, or am I better of doing that extra step with a more difficult language to 'master'?
Is Lucid (the language mentioned in and used in the Alchitry tuturials) the same as the dataflow programming language designed to experiment with non-von Neumann programming models??  https://en.wikipedia.org/wiki/Lucid_(pro..._language)

Hope to hear from someone. Would you go for a mainstream language like C or go straight to the point with VHDL or Verilog or Lucid?? Ps which one would be better for use with the Alchitry AU: VHDL or Verilog or Lucid??? I've heard Verilog is a little easier to understand/grasp then it's counterpart, but I'm taking your advice at heart Smile

Last question (I added/edited this part later to my message) Smile
Is it also possible to use Verilog (as your main programming language) and use iCEcube2/IceStorm as your toolchain for the Alchitry CU???
I'm not certain if the AU is a little overkill for the project I have in mind.
If I programm in Verilog and the CU turn out too 'light' my guess is it would be 'easy' to ugrade to the AU hardware... Or am I mistaken is my assumption?
For my use-case I need lots of FPGA boards (acting as motherboards), a cost of 50+% (compared to the AU) that act as the heart of the system is a lot of money to save Wink

With kind regards and thank you in advance, Jeroen Wolf