Are there any standard peripherals (Ethernet, SD Card, sensors, etc...) that are available which conform to these headers?

The Au and Cu are beautiful boards, but they are too tight for prototyping.  Here are a few new parts we need in the store to support REAL world applications of the Alchitry products.

1. Ribbon cables to connect the male/female IO headers (so that the Au and Br boards can be separated)
2. Standoff's allowing the boards can be separated (so components on the Br board to not short to the Au board)
3. A 1-bank (A, B, C, D) protoboard with the remaining space for electrically connected through (holes for building circuits)
4. A 2-bank (A+B, C+D, A+C, B+D) protoboard with the remaining space for electrically connected through (holes for building circuits)
5. A regular protoboard

In the photo below, you see that I am trying to connect a Raspberry Pi Zero W and two CAN Transcievers to the Au FPGA.  The second CAN Transciever had to be cut off since it hit the USB connector on the AU board and would create an electrical short.  This is why I need the ribbon cables and the standoffs.  

NOTE1: I will have to scrap the Br board and build a new one with the CAN Transcievers better placed.  
NOTE2: The mounting holes on the Au and Br boards do not align with the RPi mounting holes, so I had to expand one of the Br board holes with a file.

https://i.postimg.cc/kXZfPxkm/IMG-1903.jpg

I want to connect I/O to this board. I don't know what type of headers these are. I don't know what to search for in terms of connectors. What style of header connection is this? I can't find any type of part description for them.

I am interested in adding a WiFi-enabled microcontroller to the Au stack.  In essence, I want to use the WiFi connection to configure settings on the programmed FPGA using a tablet and a simple web page.  My fear is that the current shield design is so small, that it may be very difficult to design and build this shield.

Where can I fund the Eagle files for a blank shield?

Does anyone have advice or lessons learned on how to design this project?  (FPGA Pin selection, voltage levels, tri-state pins, ...)

Is there a preferred vendor to manufacture a new PCB?

Thank you!

Mark

I'm currently developing an application with the Au and Br using Alchitry Labs v1.1.6 in
Lucid, however I need many more switching outputs, so serial I/O expansion is needed.

The switching speed requirement is very high so SPI is my prefered choice and the
MCP23S17 16-Bit SPI Expander with serial interface is ideal for the application for 
extending multiple GPIOs. 

I'm asking for SPI implementation tips for the Au and Br as the current tutorial is
written for the Mojo, and I'm not sure how to use the spi_master compontent in
Alchitry Labs, or to add the SPI I/O to a constraints file. 

Also is there a Br constraints file for the Au?

Thanks in advance,

Mick

What happened to Alchitry.com? It keeps being unavailable and I cannot download the tools I need for the Mojo v3, neither reach the tutorials...

Any news?

I'm desperately waiting for an HDMI or VGA shield to purchase your new boards. Could you tell me when they will be available?

Your boards have great potential. Your simple design remembers me of the success of Arduino. The only lacking part is that there are few tutorials and there are few shields too. Please provide more.


Thanks

Accessing the Au board from the alchetry-labs IDE works great. 
But, neither the GUI loader, nor the standalone CLI (*) detect the device. The OS recognizes the USB board (see usb-devices).

Any pointers?

Thanks!!

(*) rebuilt version from Github with "$ g++ -o loader src/*.cpp -L ./lib/linux/ -lftd2xx -lpthread -std=c++11"

(10-25-2019, 03:49 AM)oter Wrote: Accessing the Au board from the alchetry-labs IDE works great. 
But, neither the GUI loader, nor the standalone CLI (*) detect the device. The OS recognizes the USB board (see usb-devices).

Any pointers?

Thanks!!

(*) rebuilt version from Github with "$ g++ -o loader src/*.cpp -L ./lib/linux/ -lftd2xx -lpthread -std=c++11"

Code:

$ loader -l
No devices found!
No devices found!
Couldn't find device!

# plug in

$ loader -l
Devices: 
  0: Unknown
  1: Unknown
Couldn't find device!

# OS sees device 
$ usb-devices 
...
T:  Bus=03 Lev=02 Prnt=05 Port=00 Cnt=01 Dev#=  7 Spd=480 MxCh= 0
D:  Ver= 2.00 Cls=00(>ifc ) Sub=00 Prot=00 MxPS=64 #Cfgs=  1
P:  Vendor=0403 ProdID=6010 Rev=07.00
S:  Manufacturer=Alchitry
S:  Product=Alchitry Au
S:  SerialNumber=FT3KRFFN
C:  #Ifs= 2 Cfg#= 1 Atr=80 MxPwr=500mA
I:  If#= 0 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=ff Prot=ff Driver=ftdi_sio
I:  If#= 1 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=ff Prot=ff Driver=ftdi_sio

# rule is there
$ cat /etc/udev/rules.d/99-alchitry.rules 
SUBSYSTEM!="usb|usb_device", GOTO="ft2232_rules_end"
ACTION!="add", GOTO="ft2232_rules_end"

ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6010", MODE="0666", GROUP="dialout"

LABEL="ft2232_rules_end"

# right group
$ groups `whoami`
... dialout ...

Hi,

I have a mojo v2, and a little while ago I acquired the official HDMI hat with built-in SDRAM. I'd been playing with the HDMI output quite happily, but recently tried to use the SDRAM and the example configurations don't seem to work.

The SDRAM demo just instantly lights up the LEDs to signal errors, and my custom project to read/write to the SDRAM based on UART communication always returns back the last thing I wrote to it, as if the address lines were ignored.

Are there any known issues with the SDRAM hat and the v2 of the mojo board? I thought the differences between v2 and v3 were purely around securing the USB connector better?

Does anyone have any recommendations for trying to diagnose if there's a problem with the SDRAM?

Thanks.

For better or worse I am determined to learn to use all of the Vivado tool suite. To that end I have created a set of board files that will add the Au board to Vivado's set of available boards, so that I can use the block design tools. 

To use: unzip the contents of the attached zip into: C:\Xilinx\Vivado\2019.1\data\boards\board_files\alchitry-au\1.0  (for windows users)  and restart the Vivado gui. 

Currently this includes components for: clock, reset, leds, uart, spi flash, DDR3 SDRAM, and GPIO Banks A-D.

GPIOs are implemented as interfaces on the FPGA. This looks like Vivado will treat this like a bus. I am undecided if I will leave it like this or re-implement as connectors. 

At this point I can only confirm that Vivado will create a project from this and allow the creation of a block design with the aforementioned components. I have not yet tested any projects using this set of files yet. 

While reasonable care was taken to get the pin mappings right, this was done late at night so YMMV. If you find an error, please let me know.

This was heavily modeled on (appropriated from) the Arty A7 board files.

Also attached is the spreadsheet I used to to generate the pin mapping entries for the pin file and the board file along with the Xilinx pinout. Hopefully I will have a master xdc file generated tomorrow. 

Suggestions are welcome.

Attached Files

  xc7a35tftg256pkg.xlsx (Size: 37.49 KB / Downloads: 17)
  Au_Vivado_Board_Files.zip (Size: 8.29 KB / Downloads: 18)