I contacted my shop about this but what I can find online this is really common problem...
If they refuse to replace it, what do I do?

Attached Files

  Broken LED.jpg (Size: 431.8 KB / Downloads: 93)

Since I'm new I was thinking of buying some premade shields for my board so I can concentrate on learning instead of building and soldering.

I can really only find 3 shields that is suitable for the Au+, are there more shields in the near future?

There is a Qwiic connector on the board, is there any examples of how to use that?

At the moment I have these

• SparkFun DEV-17514 Alchitry Au+ Development Board
  
• SparkFun DEV-16524 Alchitry Br Prototype Element Board
  
• SparkFun Alchitry Io Element Board
  
• Alchitry Ft Element Board (soon, ordered but not here yet)
  
• A bunch of other electronics, sensors etc that is leftovers from another project, about 20kg
  

I’m a gyrocopter pilot, a hybrid between a ”normal” airplane and a helicopter.
We send radio on the AM band and can trigger the landning lights by sending a carrier signal for 30 seconds.
What I would like to do is to listen for a specific pattern in the signal, pretty much like morse code. So if I push the send button like T-T-T-P-T-T-T-P-T-T-T where T = trigger send and P = pause.
Looks like a good thing to use the FPGA for, I need to constantly monitor the radio with as low latency as possible.

But where do I start, what externa components do I need and what area of defining modules should I look extra at to make this a real winner project?

Hi,

I'm working on a soft-core CPU design on the Alchitry Au. Ideally, I would like to use the JTAG interface from the FTDI chip to debug and program my cpu with GDB. It looks like I can make use of the BSCANE2 primitive referenced on page 175 of the 7 series FPGA user guide. However, the only example I've found of this primitive being used with the Alchitry Au is in the au-bridge git project, which seems to be undocumented. I want to check making use of this doesn't interfere with how the Alchitry loader writes the bitstream.

Additionally, it would also be nice to have some non-volatile memory to store the CPU's program in. From looking at the schematic, it looks like the on board QSPI flash is used to store the bitstream to initialise the FPGA. But the au-bridge project seems to allow programming this flash, so I would like to know if any of this can be used for user data, or if I would need my own flash chip for this.

Thanks for the help,
Charlie

I used to have an old Spartan 6 dev board but I think I killed it
So new dev board and new software to design/define my FPGA.
Where do I start except the tutorials, can I find all commands etc somewhere?
I will start with Lucid since last time I used VHDL so everything is pretty new anyway.

This is my equipment: Sparkfun DEV-17514 Alchitry Au+ Development Board

/Henrik

I am having difficulty using Alchitry Lucid for designs other that the demos.  I often get the error message when it tries to generate a Bin file that it can't find au_plus_top.bin!  I think it cannot find it because that is what it is trying to create.

I'm trying to 'stick' serial_echo with DDR to use as a data collector from two low speed sources (9600 BAUD), store them and send the data out over a smart modem (satellite modem).  Would you consider this overkill for Lucid? 

Would you consider the Au + board for commercial development?

First, I'm trying to add uarts to serial_port_echo and Alichity Labs doesn't like it.  I was able to make the additional pin assignments in Vivado and it worked.  Is there a way to run these tutorials in Vivado so I can add to the simulation without errors.  For example, when I added uart pins, described them in alchitry.acf, it left 'nulls' in place of the pin assignments in Vivado.  After filling them in, Vivado would create a usable bit stream but then I can't modify au_top_plus anymore. 

I do not see this board in Xilinx store so I can not get IP's created for it like you can other evaluation boards.  Is there a way to construct them with existing files in Alchitry Labs or am I wasting my time?  I need 3 extra rs-232 ports combined with DDR to make my project work and I am getting frustrated with trying to use Lucid outside of the demo tutorials.

Any comments would be appreciated.

Attached Files

  alchitry.xdc (Size: 1.92 KB / Downloads: 73)
  alchitryacf.txt (Size: 375 bytes / Downloads: 73)

Before starting to dig in the schematics:  the AU and AU+ FPGA can be configured via USB.
How to handle this without USB ? Are the pins (and maybe mode selection pins) available to perform FPGA configuration in SPI slave mode (e.g. from a microcontroller)

Unless I am overlooking something, it seems there is no document explaining some basic functionality of the modules and by reverse engineering the schematic it's easy to overlook something.

Can the MicroBlaze computer be accessed with Vivado/Vitis?

How many uarts can I setup with AU+? I'm hoping at least 4 to use for low speed (9600 BAUD) async sensors.