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  Blank Alchitry_AU_Shield CircuitMaker
Posted by: Initerworker - 01-01-2021, 03:02 PM - Forum: Show and Tell - No Replies

Hi everyone,

I recently had the opportunity to work on my first hardware project for a ham radio SDR Transceiver that I will explain in another thread. I need an ADDA shield, an ADC, and a DAC in Alchitry compatible shield to get my way.

I was a bit disappointed with the lack of information to create our custom shield. So, I decided to dig deep into it and made a straightforward shield design with CircuitMaker and share it with the community.

I warn you that it's my first PCB design, and all your help could be appreciated to improve this blank design.

  • A check on the connector could be helpful :-)
If you want to help me to improve the PCB design, you can ask me to collaborate on this project: If you want to use the design for your purpose, you can fork the project: If you want the connector footprint, you can use this link:
I hope that you will appreciate this opensource contribution,

Best regards,

  Alchitry Labs 1.2.5 - Vivado build log not displaying
Posted by: mdlougheed - 12-31-2020, 01:15 AM - Forum: General Questions - Replies (4)

I'm using AL 1.2.5 with Vivado. During the build, any Vivado log messages are not downing in the AL log pane. I even introduced a deliberate error in the XDC constraints file. Is there a setting in AL, or Vivado that can used to display the build log?

[Image: 103378451-2ec34b80-4a97-11eb-978a-ab449849b9ef.png]

  How to change Au master clock speed through PLL
Posted by: mdlougheed - 12-30-2020, 09:15 PM - Forum: General Questions - Replies (2)

Although it's alluded to, after searching the forum and internet too, I'm unable to find an example of changing the Au boards master clock speed through the on-board PLL.

  • 100MHz on-board clock (can be multiplied internally by the FPGA)
Can this be done using the ACF and XDC constraint files within Alchitry Labs (v1.2.5) or is there further setup within Vivado, in concert with AL that needs doing?  

For the projects I'm contemplating, it would be handy to multiply the clock by 150% and 200%.  For another it's desirable to multiply the clock by 2/3 - that is multiply by 2, then divided by 3.  The Xilinx App Note on Using Constraints hints at how to do this, however is not particularly straightforward, nor is it targeted at AL (which is understandable).

Any HOW-TO from the forum is appreciated.

  Java Development Kit Error
Posted by: itsmechuckb - 12-25-2020, 11:37 PM - Forum: Tips and Tricks - No Replies

On Windows 10 Pro, AdoptOpenJDK 11 installed, new install of Alchitry Labs. If you get a "This application requires at least Java Development Kit 1.8.0 (64-bit)" dialog when starting Alchitry Labs, it may be because you do not have the JavaSoft registry keys installed or correct for your java runtime environment. When I installed the JDK, the installer had an option to do this. It was turned off by default and I did not elect to turn it on.

This registry hack worked for me:

Windows Registry Editor Version 5.00


[HKEY_LOCAL_MACHINE\SOFTWARE\JavaSoft\Java Development Kit]

[HKEY_LOCAL_MACHINE\SOFTWARE\JavaSoft\Java Development Kit\1.11]
"JavaHome"="C:\\Program Files\\AdoptOpenJDK\\jdk-"

  JavaFx Hello World
Posted by: itsmechuckb - 12-18-2020, 07:02 PM - Forum: Show and Tell - No Replies

Here is a hello world project demonstrating the use of the register interface from a JavaFx desktop application. It uses the gradle build system to build, package, and run the app. It demonstrates a basic MVC design with JavaFx and data binding to the Alchitry board. This also demonstrates how to communicate with the Au board, as the Alchitry example shows the Mojo, which is a bit different. Code is heavily commented.

Code is here: https://github.com/chuckb/AuHelloWorld
Detailed walkthough is here: https://youtu.be/atH0MS5fdDA

  RegisterInterface gradle build support
Posted by: itsmechuckb - 12-15-2020, 11:56 PM - Forum: Tips and Tricks - No Replies

I have created a Java lib project that contains a slightly modified version of the RegisterInterface.java class. The lib is bundled up with appropriate jssc dependencies and is published to jitpack. The project is located at https://github.com/chuckb/RegisterInterface and the jitpack repo reference is located at https://jitpack.io/#com.chuckstechtalk/R...rInterface

You should be able to simply add to your gradle.build file as instructed and do a gradle run. Jssc should come down automatically.

  power from non USB source
Posted by: TechPaula - 12-14-2020, 09:28 PM - Forum: General Questions - Replies (2)

I want to power my Alchitry AU from my own PSU, but I'd still like to be able to debug it when I need.
It looks like removing the large diode on the underside near the USB connector would allow me to do this (I checked the schematics). 
Could you confirm that's the case please?

  Custom breakout board
Posted by: prebys - 12-09-2020, 09:52 PM - Forum: General Questions - Replies (2)

Has anyone made a custom breakout board for the Au?  That is, one that's a little easier to use than the Br?  Maybe with pin headers or something rather than just a solder grid.  If so, can I steal the design?


  Alchitry labs crashes Mojo V3
Posted by: rasilveroexa19 - 12-03-2020, 08:30 PM - Forum: General Questions - No Replies

Hi everyone,
I am new to the forum and also with fpga chips.
I installed the development environments for the mojo v3 card.
And everything works.
The .bin files are generated correctly whit the latest version of alchitry labs and beta version.
I only encounter a problem when I enter the "menu -> Tools -> Serial Port Monitor" which when selected immediately closes Alchitry labs, even Alchitry Loader remains blocked if I try to load the .bin file with and without the card connected.
Instead Mojo Ide and Mojo Loader works perfectly.
I'm using updated Windows 10.
When I install both Alchitry Labs and Mojo Ide I get an error message that the drivers don't have the correct language and I believe they won't install. same message if I launch the dpinst-amd64.exe file.

Thank you

  FSM Stopwatch Example
Posted by: itsmechuckb - 11-29-2020, 04:57 PM - Forum: Tips and Tricks - No Replies

In chapter 5 of Learning FPGAs, a stopwatch is built demonstrating use of the finite state machine type. I noticed that the stopwatch seemed to count too fast.

At the time of the writing, the Mojo board ran at 50 MHz. However, the Au board now runs at 100 MHz. The stopwatch was ticking every 50 ms instead of every 100ms

To count correctly in tenths of a second, the tenth_ctr must be 24 bits wide to hold 10,000,000 ticks. And, the max tick check in the RUNNING state case should be 9999999 instead of 4999999.