Hello

I am new to Lucid programming and i am testing different codes. (even though the build takes time)

I took the alchitry example with serial communication. One letter in and some code to send back the feed to the serial monitor.

In my example, the feedback is in the Always block. So here is the code i wrote in the always block.

always {
    reset_cond.in = ~rst_n; // input raw inverted reset signal
    rst = reset_cond.out;   // conditioned reset
 
    rx.rx = usb_rx;         // connect rx input
    usb_tx = tx.tx;         // connect tx output
 
    tx.new_data = rx.new_data;
    tx.data = rx.data + 1;
    tx.data = rx.data;         
    tx.block = 0;


What i am trying to do is "just" to send back 2 letters to the serial monitor, the original one (the user input) and one with the letter plus one. But i understood that the last line take preference in the always bloc, so the second line gets returned. The question how do i do that, so 2 letters is returned on input - move it out of the always block, but how?.

Next additional question would be the notion of a module, can that in other programming languages be considered as a procedure/function?

Thanks

Henrik

Hi all,

A question from an FPGA newbie: I bought a Cu, installed Alchitry Labs & IceCube2,and configured Labs so it knows where IceCube2 and the license file are located. Plugging in the Cu gives me a short flash of the 'Done' LED; voltage on the test points is 4.7V)

I can building sample projects (HelloWorld, Led to Button) without any errors, same for flashing the Cu, but: no happ flashing LEDs of any kind...

Any hints/tips/...? Am I missing something?

Thanks in advance for any info!

When I try and built the board with Alchirty Lab, I get
alchitry_imp\sbt\outputs\bitmap\cu_top_0_bitmap.bin) could not be found! The build probably failed.

I can go into the directly and run the build command and generate the bin files.  Alchirty still says it cant find them.  I can use the Alchirty Loader to flash it.

Hi admin,
I just wanted to let you know I noticed a typo error in an URL from the Tutorials (Backgrounds) section.
When clicking on 'Addition' you are directed to: https://alchitry.com/additoin... it has to be: https://alchitry.com/addition (the latter works )


Cheers, Jeroen

I'm trying to upload my build code to my alchitry-CU FPGA board threw apio using iceprog on windows.

I have tried and think proved that rx.data cannot cross the case (state.q) boundary.  I can use led = rx.data; before the case statement and the appropriate bits light up.  If I put the same led = rx.data after the case statement, it will not light any lights.

So,

led = rx.data;     /lights appropriate bits

case(state.q) {
  mig.mem_in.en = 1;
  mig.mem_in.cmd = 0;
  mig.mem_in.wr_data = rx.data;
  led = rx.data;                                  //does nothing!

Please explain.  I have spent over a week trying this and that and the only conclusion is there is a problem with Lucid.  If it's a bug, please let me know so I stop spinning my wheels.

Thank you,
howdyrichard

I thought I found an answer - wrong.  I tried making a var testbyte and then tying it to rx.data, but that did not work either.  How do I get a byte from rx_uart into a case(state.q) in au_top_plus.luc?  It's the case structure from DDR3 tutorial.

error produced in Alchitry Labs:
Bin file (C:\Users\howdy\Documents\Alchitry\Xilinx\DDR_Test\work\vivado\DDR_Test\DDR_Test.runs\impl_1\au_plus_top_0.bin) could not be found! The build probably failed.

This is a standard error when something is wrong, and "No errors detected" when checking.

This is the error in Vivado:
[Synth 8-1749] cannot have packed dimensions of type integer ["C:/Users/howdy/Documents/Alchitry/Xilinx/DDR_Test/work/vivado/DDR_Test/DDR_Test.srcs/sources_1/imports/verilog/au_plus_top_0.v":163]

This is what I tried:
var testbyte[8];

always {
/* Clock Wizard Connections */
clk_wiz.clk_in1 = clk; // 100MHz in
clk_wiz.reset = !rst_n; // reset signal

rx.rx = usb_rx; // connect rx input
usb_tx = tx.tx; // connect tx output

rx1.rx = dcs_rx;
// dcs_tx = tx1.tx;


then near the case:

testbyte = rx1.data; //rx1.data is from a second uart, the original rx.data is still used as USB_RX

case (state.q) {
state.WRITE_DATA:
mig.mem_in.wr_en = 1;
mig.mem_in.wr_data = testbyte; //trying to use this var to transfer received byte from uart_rx1. Using rx1.data here does nothing but I do not get any errors.
if (mig.mem_out.wr_rdy)
state.d = state.WRITE_CMD;

If I do not specify size of var testbyte[8]; and just say var testbyte; I get this warning from Lucid:


Line 78, Column 15 : The signal "rx1.data" is wider than "testbyte" and the most significant bits will be dropped

I've been noticing that when I clone a project, rename it and save it in a completely different directory and use this 'new' cloned file, the old source file also gets updated with my new experiments!  Why?

I'm currently working the new parser for Lucid V2. This will be a major update to the Lucid language and will bring many breaking changes.

Currently, these are the changes I'm working on.

• Optional semicolons. Following the trend of many modern languages, new lines can be used in place of semicolons.
  
• Removal the 'var' type. This type never really made much use sense to me. It is functionally equivalent to 'sig' that is 32 bits wide.
  
• Replace the 'for' loop with a 'repeat' statement. This will likely have the syntax like "repeat(5: sig) { }" where "sig" would be assigned 0,1,2,3,4 depending on the iteration. For statements are kind of a weird thing to have in hardware since they must have a fixed number of iterations. The "C" style loop used currently and by Verilog is a bit cumbersome and can easily be written to not be a fixed number of iterations.
  

Hello,

I'm still using the Mojo-board and installed Xilinx ISE 14.7 on Ubuntu 20.04 (64 bits).
That was running fine until I wanted to generate an IP-core.
The core generator failed every time.
After a long search I finally found the solution on the following web-site: https://wiki.archlinux.org/title/Xilinx_ISE_WebPACK
I had to replace the java-runtime with the java6 runtime as described at the end of the web-site under 'CORE Generator fails to generate core', solution #2.
To be sure I also applied solution #1.

Have a nice day!

Ferdinand Postema