Welcome, Guest
You have to register before you can post on our site.



Search Forums

(Advanced Search)

Forum Statistics
» Members: 1,142
» Latest member: goro
» Forum threads: 246
» Forum posts: 723

Full Statistics

Online Users
There are currently 61 online users.
» 0 Member(s) | 58 Guest(s)
Baidu, Bing, Google

Latest Threads
Closing the Forum
Forum: Announcements
Last Post: alchitry
10-31-2022, 02:42 PM
» Replies: 0
» Views: 1,804
Trouble with shift operto...
Forum: General Questions
Last Post: gln
10-26-2022, 08:29 AM
» Replies: 0
» Views: 1,317
Alchitry Au+ / ft600
Forum: General Questions
Last Post: Andrea1806
10-12-2022, 03:21 PM
» Replies: 0
» Views: 989
Cannot program new Amazon...
Forum: General Questions
Last Post: dkaleta
10-10-2022, 06:01 PM
» Replies: 1
» Views: 1,525
I2C Controller example ne...
Forum: General Questions
Last Post: dkaleta
10-09-2022, 01:52 AM
» Replies: 0
» Views: 1,292
Alchitry Board to Board C...
Forum: General Questions
Last Post: LMN128
09-30-2022, 08:40 AM
» Replies: 1
» Views: 1,764
CU board wont program
Forum: General Questions
Last Post: sfnagle
09-27-2022, 05:17 AM
» Replies: 4
» Views: 3,684
CuBr pins
Forum: Tips and Tricks
Last Post: jldevictoria
09-27-2022, 03:31 AM
» Replies: 3
» Views: 7,709
Lucid build via command-l...
Forum: General Questions
Last Post: SoCalCFI
09-15-2022, 06:02 AM
» Replies: 0
» Views: 988
Bin file not found - but ...
Forum: General Questions
Last Post: billh
08-27-2022, 08:48 PM
» Replies: 0
» Views: 1,014

  Always block
Posted by: aab163 - 03-25-2022, 11:51 AM - Forum: General Questions - Replies (1)


I am new to Lucid programming and i am testing different codes. (even though the build takes time)

I took the alchitry example with serial communication. One letter in and some code to send back the feed to the serial monitor.

In my example, the feedback is in the Always block. So here is the code i wrote in the always block.

always {
    reset_cond.in = ~rst_n; // input raw inverted reset signal
    rst = reset_cond.out;   // conditioned reset
    rx.rx = usb_rx;         // connect rx input
    usb_tx = tx.tx;         // connect tx output
    tx.new_data = rx.new_data;
    tx.data = rx.data + 1;
    tx.data = rx.data;         
    tx.block = 0;

What i am trying to do is "just" to send back 2 letters to the serial monitor, the original one (the user input) and one with the letter plus one. But i understood that the last line take preference in the always bloc, so the second line gets returned. The question how do i do that, so 2 letters is returned on input - move it out of the always block, but how?.

Next additional question would be the notion of a module, can that in other programming languages be considered as a procedure/function?


Henrik Smile

  Can't get the Cu to work...
Posted by: Gleekzorp - 03-19-2022, 02:33 PM - Forum: General Questions - Replies (3)

Hi all,

A question from an FPGA newbie: I bought a Cu, installed Alchitry Labs & IceCube2,and configured Labs so it knows where IceCube2 and the license file are located. Plugging in the Cu gives me a short flash of the 'Done' LED; voltage on the test points is 4.7V)

I can building sample projects (HelloWorld, Led to Button) without any errors, same for flashing the Cu, but: no happ flashing LEDs of any kind...

Any hints/tips/...? Am I missing something?

Thanks in advance for any info!

  CU board wont program
Posted by: bstaton - 03-17-2022, 11:43 PM - Forum: General Questions - Replies (4)

When I try and built the board with Alchirty Lab, I get
alchitry_imp\sbt\outputs\bitmap\cu_top_0_bitmap.bin) could not be found! The build probably failed.

I can go into the directly and run the build command and generate the bin files.  Alchirty still says it cant find them.  I can use the Alchirty Loader to flash it.

  URL typo error in the Alchitry Tutorials (Background) section
Posted by: Joena - 03-13-2022, 02:38 PM - Forum: General Questions - Replies (1)

Hi admin,
I just wanted to let you know I noticed a typo error in an URL from the Tutorials (Backgrounds) section.
When clicking on 'Addition' you are directed to: https://alchitry.com/additoin... it has to be: https://alchitry.com/addition (the latter works Wink)

Cheers, Jeroen

  iceprog - Can't find iCE FTDI USB device with Alchitry CU
Posted by: Lopfi - 03-03-2022, 09:13 PM - Forum: General Questions - No Replies

I'm trying to upload my build code to my alchitry-CU FPGA board threw apio using iceprog on windows.

apio upload

which then executes
iceprog -d i:0x0403:0x6010:0 hardware.bin

And the output is
Can't find iCE FTDI USB device (device string i:0x0403:0x6010:0).
scons: *** [upload] Error 2

I have installed the libusbk driver and also tested uploading with the same cable on another pc with the standard drivers and the provided IDE Alchitry Labs in combination with iceCube2 but I really wanted to use the open source alternative instead.

  Moving data into a case statement
Posted by: howdyrichard - 02-22-2022, 12:33 AM - Forum: General Questions - Replies (3)

I have tried and think proved that rx.data cannot cross the case (state.q) boundary.  I can use led = rx.data; before the case statement and the appropriate bits light up.  If I put the same led = rx.data after the case statement, it will not light any lights.


led = rx.data;     /lights appropriate bits

case(state.q) {
  mig.mem_in.en = 1;
  mig.mem_in.cmd = 0;
  mig.mem_in.wr_data = rx.data;
  led = rx.data;                                  //does nothing!

Please explain.  I have spent over a week trying this and that and the only conclusion is there is a problem with Lucid.  If it's a bug, please let me know so I stop spinning my wheels.

Thank you,

  Passing variables into case statements
Posted by: howdyrichard - 02-20-2022, 04:47 PM - Forum: General Questions - No Replies

I thought I found an answer - wrong.  I tried making a var testbyte and then tying it to rx.data, but that did not work either.  How do I get a byte from rx_uart into a case(state.q) in au_top_plus.luc?  It's the case structure from DDR3 tutorial.

error produced in Alchitry Labs:
Bin file (C:\Users\howdy\Documents\Alchitry\Xilinx\DDR_Test\work\vivado\DDR_Test\DDR_Test.runs\impl_1\au_plus_top_0.bin) could not be found! The build probably failed.

This is a standard error when something is wrong, and "No errors detected" when checking.

This is the error in Vivado:
[Synth 8-1749] cannot have packed dimensions of type integer ["C:/Users/howdy/Documents/Alchitry/Xilinx/DDR_Test/work/vivado/DDR_Test/DDR_Test.srcs/sources_1/imports/verilog/au_plus_top_0.v":163]

This is what I tried:
var testbyte[8];

always {
/* Clock Wizard Connections */
clk_wiz.clk_in1 = clk; // 100MHz in
clk_wiz.reset = !rst_n; // reset signal

rx.rx = usb_rx; // connect rx input
usb_tx = tx.tx; // connect tx output

rx1.rx = dcs_rx;
// dcs_tx = tx1.tx;

then near the case:

testbyte = rx1.data; //rx1.data is from a second uart, the original rx.data is still used as USB_RX

case (state.q) {
mig.mem_in.wr_en = 1;
mig.mem_in.wr_data = testbyte; //trying to use this var to transfer received byte from uart_rx1. Using rx1.data here does nothing but I do not get any errors.
if (mig.mem_out.wr_rdy)
state.d = state.WRITE_CMD;

If I do not specify size of var testbyte[8]; and just say var testbyte; I get this warning from Lucid:

Line 78, Column 15 : The signal "rx1.data" is wider than "testbyte" and the most significant bits will be dropped

  Cloning a project
Posted by: howdyrichard - 02-20-2022, 03:38 PM - Forum: General Questions - Replies (2)

I've been noticing that when I clone a project, rename it and save it in a completely different directory and use this 'new' cloned file, the old source file also gets updated with my new experiments!  Why?

Exclamation Lucid V2
Posted by: alchitry - 02-02-2022, 11:24 PM - Forum: General Questions - Replies (10)

I'm currently working the new parser for Lucid V2. This will be a major update to the Lucid language and will bring many breaking changes.

Currently, these are the changes I'm working on.

  • Optional semicolons. Following the trend of many modern languages, new lines can be used in place of semicolons.
  • Removal the 'var' type. This type never really made much use sense to me. It is functionally equivalent to 'sig' that is 32 bits wide.
  • Replace the 'for' loop with a 'repeat' statement. This will likely have the syntax like "repeat(5: sig) { }" where "sig" would be assigned 0,1,2,3,4 depending on the iteration. For statements are kind of a weird thing to have in hardware since they must have a fixed number of iterations. The "C" style loop used currently and by Verilog is a bit cumbersome and can easily be written to not be a fixed number of iterations.
I'd love some feedback on these changes and any other potential changes you'd like to see make it into this update.

The rest of this post is the nitty gritty of the update.

The original Lucid parser has had feature after feature tacked on to where it is a bit of a mess today. Originally, it only attempted to figure out the width of signals. Then I added stuff that would parse constant expressions so custom functions could be added. Now I want a general interpreter that could be used to build a simulator. This was the motivation behind the full overhaul.

The original parser is broken into a handful of modules here https://github.com/alchitry/Alchitry-Lab...ools/lucid

The main parent is the LucidExtractor. This deals with all the declarations of stuff like modules, dffs, fsms, etc.
The BitWidthChecker attempts to figure out how wide each signal is. It is responsible for giving errors for situations like when you try to assign a struct to an array.
The ConstExprParser was original used to parse constant expressions for functions but has slowly outgrown that role to general expression parsing.
The BoundsParser parses array bounds (like [5:1] or [0+:3])
The ConstParser builds a list of constants declared
The ParamsParser builds a list of parameters declared

There are also a handful of other helper parsers like the LucidGlobalExtractor that parses globals in an initial pass of all the files.

These are all weirdly interdependent which is one of the goals to fix for the new parse.

Currently, the V2 parser handles expressions. I now need to add the rest (variable declarations, various block parsing, global statements, etc)

Its code can be found here https://github.com/alchitry/Alchitry-Lab...rs/lucidv2
The ExprParser is responsible for assigning a Value to every expression. This combines the functionality of the BitWidthChecker and ConstExprParser as these were often redundant. The Value type has an associated width to it and can be an UndefinedValue that still has a width which covers the cases that the BitWidthChecker used to deal with when ConstExprParser couldn't figure out a value.

I also plan to roll some of the small parsers into ExprParser such as BoundsParser (which I added today). Having multiple parsers that are interdependent makes using them difficult.

Information CORE Generator fails to generate core
Posted by: Ferdinand Postema - 01-26-2022, 12:12 AM - Forum: Tips and Tricks - No Replies


I'm still using the Mojo-board and installed Xilinx ISE 14.7 on Ubuntu 20.04 (64 bits).
That was running fine until I wanted to generate an IP-core.
The core generator failed every time.
After a long search I finally found the solution on the following web-site: https://wiki.archlinux.org/title/Xilinx_ISE_WebPACK
I had to replace the java-runtime with the java6 runtime as described at the end of the web-site under 'CORE Generator fails to generate core', solution #2.
To be sure I also applied solution #1.

Have a nice day!

Ferdinand Postema