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Latest Threads
Alchitry Labs not playing...
Forum: General Questions
Last Post: Tyrving
04-03-2021, 11:11 PM
» Replies: 0
» Views: 157
Alchitry-Cu first tutori...
Forum: General Questions
Last Post: wing
03-25-2021, 12:33 PM
» Replies: 2
» Views: 231
Which Ubuntu and JRE vers...
Forum: General Questions
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03-24-2021, 05:51 PM
» Replies: 0
» Views: 179
FT2232HQ Configuration (A...
Forum: General Questions
Last Post: Rory
03-21-2021, 05:59 AM
» Replies: 1
» Views: 281
DRIVE strength and SLEW r...
Forum: General Questions
Last Post: Rory
03-21-2021, 05:17 AM
» Replies: 0
» Views: 108
Mojo v3 HDMI SHield Eagle...
Forum: General Questions
Last Post: Helder
03-18-2021, 01:32 PM
» Replies: 2
» Views: 311
Thermal issues? + More
Forum: General Questions
Last Post: Tyrving
02-20-2021, 07:52 PM
» Replies: 2
» Views: 329
Mojo V3 Lucid Sdram Test ...
Forum: General Questions
Last Post: tistructor
02-17-2021, 07:37 PM
» Replies: 1
» Views: 221
7 Seg Display Letters?
Forum: General Questions
Last Post: alchitry
02-16-2021, 03:34 PM
» Replies: 1
» Views: 258
Alchitry Labs not recogni...
Forum: General Questions
Last Post: alchitry
02-16-2021, 03:21 PM
» Replies: 2
» Views: 370

  Mojo V3 change pins for 16Bit sdram
Posted by: tistructor - 01-20-2021, 09:54 AM - Forum: General Questions - No Replies

I wanted to ask for information:
Can the I / O pins used in the SDRAM shield for the mojo be changed?
I wanted to manage a 16-bit module and a different configuration of the mojo pins is needed to achieve a good pcb design.

I checked the spartan-6 lx9 datasheet and I don't think there are any problems with the pins I'm using.

This is the pins list:
DQO -> P94
DQ1 -> P95
DQ2 -> P97
DQ3 -> P98
DQ4 -> P99
DQ5 -> P100
DQ6 -> P101
DQ7 -> P102
DQ8 -> P7
DQ9 -> P8
DQ10 -> P9
DQ11 -> P10
DQ12 -> P11
DQ13 -> P12
DQ14 -> P14
DQ15 -> P15

A0 -> P118
A1 -> P119
A2 -> P120
A3 -> P121
A4 -> P138
A5 -> P139
A6 -> P140
A7 -> P141
A8 -> P142
A9 -> P143
A10 -> P117
A11 -> P144
A12 -> P1

DQML -> 104
WE -> 105
CAS -> 111
RAS -> 112
CS -> 114
BA0 -> 115
BA1 -> 116

CLK -> P5
DQMH -> P6
CKE -> P2


thank you


  Thermal issues? + More
Posted by: Tyrving - 01-18-2021, 10:05 PM - Forum: General Questions - Replies (2)

My backordered AU starter kit just arrived, and when I plug it in, all seems well, and the LEDs do what I expect, after waiting a sec from when I plug it in. I noticed the FPGA getting toasty, although nothing painful to touch, very quickly, and am wondering if this is expected.

Assorted questions:
The default program works fine, doing the nifty (ripple? Not sure what to call this) animation. Pressing reset will make the second LED go solid for about 1/2 second, then it will begin alternating even/odd LEDs as I assume is intended. I am guessing this is from the necessary reprogramming of the (iirc volitile sram?) LUTs from the onboard flash, but I don't know a whole lot about this.
How much current can the BR drive? I don't expect it to power a relay or anything, but this would be useful to know. Forgive me if this is in the schematic or somewhere else I should have checked before posting.
Out of curiosity, what will happen to the pick and place/other tools you purchased to manufacture the boards now that Sparkfun is doing that?
Lastly, the 7-segs on the IO element have a faint glow when board is plugged in. Normal? Product of my EMI-ridden workspace?
Also, could this EMI cause any other issues potential issues using long wires and such from the BR element later on? I'm not exaggerating about the amount of EMI, it has begun to cause issues with my USB keyboard, camera, and mouse.  I've got some ferrite chokes on the way, but patience is a virtue I do not possess.

Have a wonderful day, and a preemptive thank you!

  Mojo v3 HDMI SHield Eagle Files?
Posted by: Helder - 01-18-2021, 09:10 PM - Forum: General Questions - Replies (2)

Hi I am looking for the HDMI Shield Eagle files which I know are no longer being made but many of the other shields have the eagle files available I was hping maybe they were available as well but there is only a schematic.


My plan is to replace the SRAM chip on this shield to a 16bit one so it would be easier to get higher resolutions with the extra SRAM.

Thank you.

Question Platform Choice: Mojo V3 or Other?
Posted by: Back2Basics - 01-17-2021, 02:44 AM - Forum: General Questions - Replies (1)

I'm starting graduate school soon, and my first class relates to learning/designing parallel computing architectures. The course is project-based, where I am free to select a programming language and platform of our choosing. I have a Mojo V3, SDRAM shield, and clock/viz shield that I purchased from (then) EmbeddedMicro a long time ago but sadly never got put to good use. I'm considering using the Mojo V3 for my coursework, but I don't know how to properly assess whether building on it or a newer platform would be the better idea.

I wasn't able to get any specific recommendations from faculty, and the university labs don't appear to have open access to FPGA development hardware at this time. I have a little experience working with Verilog, but not enough where I can claim competency on any specific platform. What would be an effective way to begin determining what FPGA architectures and/or development kits I should consider?

  Error when Debugging with Alchitry Labs 1.2.5
Posted by: Jay8ee - 01-12-2021, 03:50 PM - Forum: General Questions - Replies (2)


When I click debug > choose the signals I want in the wave capture, I get the following error:

java.lang.NullPointerException: Cannot invoke "com.alchitry.labs.parsers.lucid.parser.LucidParser$NameContext.getText()" because the return value of "com.alchitry.labs.parsers.lucid.parser.LucidParser$Output_decContext.name()" is null
    at com.alchitry.labs.parsers.tools.lucid.toVerilog.LucidToVerilog.exitOutput_dec(LucidToVerilog.java:477)
    at com.alchitry.labs.parsers.lucid.parser.LucidParser$Output_decContext.exitRule(LucidParser.java:767)
    at com.alchitry.labs.tools.ParseTreeMultiWalker.exitRule(ParseTreeMultiWalker.java:49)
    at com.alchitry.labs.tools.ParseTreeMultiWalker.walk(ParseTreeMultiWalker.java:31)
    at com.alchitry.labs.tools.ParseTreeMultiWalker.walk(ParseTreeMultiWalker.java:29)
    at com.alchitry.labs.tools.ParseTreeMultiWalker.walk(ParseTreeMultiWalker.java:29)
    at com.alchitry.labs.tools.ParseTreeMultiWalker.walk(ParseTreeMultiWalker.java:29)
    at com.alchitry.labs.tools.ParseTreeMultiWalker.walk(ParseTreeMultiWalker.java:29)
    at com.alchitry.labs.tools.ParserCache.walk(ParserCache.java:127)
    at com.alchitry.labs.parsers.tools.lucid.toVerilog.LucidToVerilog.convert(LucidToVerilog.java:50)
    at com.alchitry.labs.project.builders.ProjectBuilder.getVerilogFile(ProjectBuilder.java:187)
    at com.alchitry.labs.project.builders.ProjectBuilder.getVerilogFiles(ProjectBuilder.java:341)
    at com.alchitry.labs.project.builders.VivadoBuilder.generateProjectFile(VivadoBuilder.java:120)
    at com.alchitry.labs.project.builders.VivadoBuilder.projectBuilder(VivadoBuilder.java:33)
    at com.alchitry.labs.project.builders.ProjectBuilder.build(ProjectBuilder.java:152)
    at com.alchitry.labs.project.Project$build$1.invokeSuspend(Project.kt:1260)
    at kotlin.coroutines.jvm.internal.BaseContinuationImpl.resumeWith(ContinuationImpl.kt:33)
    at kotlinx.coroutines.DispatchedTask.run(DispatchedTask.kt:56)
    at kotlinx.coroutines.scheduling.CoroutineScheduler.runSafely(CoroutineScheduler.kt:571)
    at kotlinx.coroutines.scheduling.CoroutineScheduler$Worker.executeTask(CoroutineScheduler.kt:738)
    at kotlinx.coroutines.scheduling.CoroutineScheduler$Worker.runWorker(CoroutineScheduler.kt:678)
    at kotlinx.coroutines.scheduling.CoroutineScheduler$Worker.run(CoroutineScheduler.kt:665)

Please note that my project builds fine normally. It is basically a blank base AU project (Verilog).

Any ideas? 


  Programming Alchitry Au directly from Vivado
Posted by: tntodorov - 01-12-2021, 06:41 AM - Forum: General Questions - Replies (1)

Is it possible to program the Au directly from Vivado?

If anyone has done it, or has a pointer to more information, it will be very much appreciated! Alternatively, please explain why it is not possible...


  Wave Capture Example Project
Posted by: mdlougheed - 01-10-2021, 09:01 PM - Forum: General Questions - Replies (1)

This 2016 Alchitry blog post mentions a debug wave capture example project, however there is no link to it.

For the Au board, I'm exploring the debug interface and would appreciate learning the proper way to set up wave capture for debug.


  Alchitry Au+ new board
Posted by: LMN128 - 01-10-2021, 05:05 PM - Forum: General Questions - Replies (1)

Congratulation for new bigger Au board. Is there any change except FPGA chip, please?

  Some confusion about Au DDR3 interface
Posted by: fungineering_101 - 01-07-2021, 07:15 PM - Forum: General Questions - Replies (1)

Hi - I'm trying to work out exactly how this is addressed, and something's wrong with my math.

Starting assumption - it's a 256MB part, and has a 28-bit address field - which is really a 25-bit field since the last 3 are reserved as 0s for ordering.  So there are 2**25 => 33,554,432 distinct addresses.  Which is each address was for an 8-byte block, that multiplies back to 256 MB - but the data in bus is 128-bits / 16 bytes wide?

Do these overlap?  Can I write to address '1' by writing 9 bytes into address '0'?

Alternatively, if it was really a 24-bit address field, with each address being a 16-byte/128-bit block, that would seem like a simpler explanation, if maybe the part interface is shared with a 512MB module and the MSB is unused in the Au's part.

  Register Interface Bug?
Posted by: itsmechuckb - 01-05-2021, 12:55 AM - Forum: General Questions - Replies (1)

I am looking into why, but if anyone else has noticed, please reply. I am using the RegisterInterface.java class to communicate with the reg_interface.luc module. Things are working fine, except when I send 1 integer from the host to the Au using the write method. Multiple integers within the same session work fine. But when one integer is sent, (open port, send one int, close port) I do not get the MSB within the integer transmitted.