Welcome, Guest
You have to register before you can post on our site.



Search Forums

(Advanced Search)

Forum Statistics
» Members: 710
» Latest member: 007mcafeee
» Forum threads: 193
» Forum posts: 558

Full Statistics

Online Users
There are currently 20 online users.
» 0 Member(s) | 19 Guest(s)

Latest Threads
MOJO sdram
Forum: General Questions
Last Post: alialaei
Yesterday, 03:54 PM
» Replies: 0
» Views: 6
Vivado and licensing
Forum: General Questions
Last Post: Tyrving
10-08-2021, 04:24 PM
» Replies: 1
» Views: 99
Direct JTAG programming d...
Forum: General Questions
Last Post: alchitry
10-07-2021, 05:20 PM
» Replies: 1
» Views: 122
Starting with Alchitry Au...
Forum: General Questions
Last Post: alchitry
10-07-2021, 04:49 PM
» Replies: 1
» Views: 110
Au plus and DDR3 Tutorial
Forum: General Questions
Last Post: alchitry
09-24-2021, 04:57 PM
» Replies: 4
» Views: 669
Alchitry Labs not working...
Forum: General Questions
Last Post: mdlougheed
09-08-2021, 12:12 AM
» Replies: 3
» Views: 847
Could not detect an Au!
Forum: General Questions
Last Post: satheesh_s
07-23-2021, 01:51 AM
» Replies: 6
» Views: 2,839
LEDs on Io Breakout Board...
Forum: Tips and Tricks
Last Post: alchitry
07-22-2021, 02:35 PM
» Replies: 2
» Views: 531
Alchitry labs crashes Moj...
Forum: General Questions
Last Post: alchitry
07-22-2021, 02:33 PM
» Replies: 1
» Views: 829
DDR3 speed in example
Forum: General Questions
Last Post: alchitry
07-22-2021, 02:31 PM
» Replies: 3
» Views: 1,458

  Alchitry Labs not working at all
Posted by: jm.sellier - 05-12-2021, 08:09 PM - Forum: General Questions - Replies (3)


I recently bought an Alchitry Au and I am planning to use Alchitry Labs to program it. Unfortunately, for reasons which I really can't understand, I cannot synthesis anything from this IDE. When I push the little hammer button, the IDE says "Starting Vivado..." but then it stays like this forever.

Let me provide more info below :

- I am using Vivado 2020.1 and it works perfectly with the Alchitry Au board,
- My java is updated to the latest version, i.e. 1.8.0_291-b10,
- The Alchitry Labs version is 1.2.6,
- Everything is installed on a regularly updated Windows 10 machine.

Any idea why I am not able to build anything from this IDE? Obviously, I will provide more information, if necessary, to whoever wants to help me.


  cu_top_0_bitmap not found
Posted by: D22 - 05-11-2021, 02:36 PM - Forum: General Questions - Replies (5)

Tried to build 1st example for a Cu board using Lucid when I got this error:

Bin file (C:\Users\David\Documents\alchitry\CuLEDtoButton\work\alchitry_imp\sbt\outputs\bitmap\cu_top_0_bitmap.bin) could not be found! The build probably failed.

I see in the forum where one fellow seemed to solve the problem but he wasn't kind enough to provide the solution!!!!!

  AU - DDR3 PIn use
Posted by: TechPaula - 05-09-2021, 08:10 PM - Forum: General Questions - Replies (1)

I'm having some problems running the "memory interface generator" in vivado.
I'm trying to configure the DDR3 basic on the schematic and XDC files, however I get an error;

ERROR : The port ddr3_addr[5] is allocated in the bank 15 where the input ports are allocated. Enable the Internal Vref to use the Vref as GPIO.

now I believe, I need these lines;
set_property INTERNAL_VREF 0.7 [get_iobanks 65]
set_property INTERNAL_VREF 0.84 [get_iobanks 67]
but with those in the projects XDC file and with the project built, I still get the error.

I've tried this thread - https://forum.alchitry.com/thread-234.html
But sadly the project that is created is blank and has no mig_7series_0 module.

Could you explain how to configure this to work please?

  vitis/vivado compatibility
Posted by: oldman95 - 05-06-2021, 09:36 PM - Forum: General Questions - Replies (1)

Does Alchitry have the hardware description file for the Au board?  I think it is referred to as an xsa file.

  Alchitry Cu tutorial not working
Posted by: ekellmyer - 04-30-2021, 09:25 PM - Forum: General Questions - Replies (1)

Absolute beginner to FPGA programming here. Trying to do the tutorial for my first FPGA project for the Cu, but my project won't build. I keep getting the message "Bin file (C:\Users\User\Documents\Alchitry\LED\work\alchitry_imp\sbt\outputs\bitmap\cu_top_0_bitmap.bin) could not be found! The build probably failed."
I'm on Labs version 1.2.6 and iceCube2 version 2017.1 on Windows.

Any help would be greatly appreciated.

  BR shield short?
Posted by: usherman20 - 04-30-2021, 06:27 AM - Forum: General Questions - Replies (1)

Hi all,

I'm currently playing with my new CU and BR boards. I am running into a strange issue though: I can program the bare CU board fine, but cannot upload when the BR board is mounted. I uploaded the counter example and the builtin leds blink fine. I also have the IO shield. The IO shield example program works as expected, and I can program with the IO shield mounted. Trying to program the CU with the bare BR board fails with this error:

Extended device string lenght is 0xff. This is likely an error. Ignoring...
com.alchitry.labs.hardware.usb.ftdi.Mpsse$MpsseException: Flash ID was 0xFFFFFFFF expected 0xEF401600
    at com.alchitry.labs.hardware.usb.ftdi.LatticeSpi.flashReadId(LatticeSpi.java:150)
    at com.alchitry.labs.hardware.usb.ftdi.LatticeSpi.writeBin(LatticeSpi.java:284)
    at com.alchitry.labs.hardware.loaders.CuLoader.program(CuLoader.java:54)
    at com.alchitry.labs.hardware.loaders.ProjectLoader.load(ProjectLoader.java:61)
    at com.alchitry.labs.project.Project$load$1.invokeSuspend(Project.kt:1297)
    at kotlin.coroutines.jvm.internal.BaseContinuationImpl.resumeWith(ContinuationImpl.kt:33)
    at kotlinx.coroutines.DispatchedTask.run(DispatchedTask.kt:56)
    at kotlinx.coroutines.scheduling.CoroutineScheduler.runSafely(CoroutineScheduler.kt:571)
    at kotlinx.coroutines.scheduling.CoroutineScheduler$Worker.executeTask(CoroutineScheduler.kt:738)
    at kotlinx.coroutines.scheduling.CoroutineScheduler$Worker.runWorker(CoroutineScheduler.kt:678)
    at kotlinx.coroutines.scheduling.CoroutineScheduler$Worker.run(CoroutineScheduler.kt:665)
Both pins D36 and D39 (config reset, reset) are high. One further complication - if I mount the BR board on the CU while the CU counter led blink program is running, it continues to run fine (and probing the led pads on the BR match the lights fine). However, if I remove power and plug it back in while the BR is mounted, the loaded program _will not run_. Instead, I only see the on board leds shining very dimly. I don't feel any obvious hot spots in the board to indicate shorts, and I've probed 3.3V, 5V, and Gnd for shorts, and come up with nothing. Any other ideas??
Thanks, Jarrett

  routing DDR3 fails with invalid clock parameters
Posted by: agemoz - 04-20-2021, 07:37 PM - Forum: General Questions - Replies (2)

Has anyone gotten the DDR3 module to work with the alchrity AU+ board?  I followed the tutorial at


and also just ran a pure verilog version on Vivado, neither one of which appears to work. Lot's of other stuff is working on this board, but I've had no luck with the DDR3.

I have the xilinx DDR3 module instantiated, along with a MMCM clock synthesis generating 100Mhz input, 100Mhz to sys_clk_i and 200Mhz to clk_ref_i.  Vivado synthesizes without error, but routing DRC complains about this:

[DRC PDRC-34] MMCM_adv_ClkFrequency_div_no_dclk: The computed value 200.000 MHz (CLKIN1_PERIOD, net pll_clk3) for the VCO operating frequency of the MMCME2_ADV site MMCME2_ADV_X0Y2 (cell i_mig_7series_0/u_mig_7series_0_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i) falls outside the operating range of the MMCM VCO frequency for this device (600.000 - 1200.000 MHz). The computed value is (CLKFBOUT_MULT_F * 1000 / (CLKINx_PERIOD * DIVCLK_DIVIDE)). Please run update_timing to update the MMCM settings. If that does not work, adjust either the input period CLKINx_PERIOD (40.000000), multiplication factor CLKFBOUT_MULT_F (8.000000) or the division factor DIVCLK_DIVIDE (1), in order to achieve a VCO frequency within the rated operating range for this device.

Looks like the internals of the Xilinx DDR3 module expects something different for the sys_clk_i and clk_ref_i frequencies.  It suggests updating timing (Vivado wont allow me to do this), and setting the CLKIN1_PERIOD and other parameters manually is grayed out. 

Any suggestions? I tried to do an example with Lucid following the tutorial, but that failed as well--it is getting confused what the top level file is--never finds it--and never builds.

Here's the top level source instantiation

mig_7series_0 i_mig_7series_0
   .ddr3_dq             (ddr3_dq),
   .ddr3_dqs_n          (ddr3_dqs_n),
   .ddr3_dqs_p          (ddr3_dqs_p),
   .ddr3_addr           (ddr3_addr),
   .ddr3_ba             (ddr3_ba),
   .ddr3_ras_n          (ddr3_ras_n),
   .ddr3_cas_n          (ddr3_cas_n),
   .ddr3_we_n           (ddr3_we_n),
   .ddr3_reset_n        (ddr3_reset_n),
   .ddr3_ck_p           (ddr3_ck_p),
   .ddr3_ck_n           (ddr3_ck_n),
   .ddr3_cke            (ddr3_cke),
   .ddr3_cs_n           (ddr3_cs_n),
   .ddr3_dm             (ddr3_dm),
   .ddr3_odt            (ddr3_odt),

   .sys_clk_i           (sysclk),
   .clk_ref_i           (sysclk_2x),
   .app_addr            (dev_ddr3_addr),
   .app_cmd             ({2'h0,~dev_ddr3_wr}),
   .app_en              (dev_ddr3_en),
   .app_wdf_data        (dev_ddr3_wdata),
   .app_wdf_end         (1),
   .app_wdf_mask        (0),
   .app_wdf_wren        (dev_ddr3_wr),
   .app_rd_data         (dev_ddr3_rdata),
   .app_rd_data_end     (1),
   .app_rd_data_valid   (dev_ddr3_rd_data_valid),
   .app_rdy             (dev_ddr3_rdy),
   .app_wdf_rdy         (dev_ddr3_wdf_rdy),
   .app_sr_req          (0),
   .app_ref_req         (0),
   .app_zq_req          (0),
   .app_sr_active       (dev_ddr3_sr_active),
   .app_ref_ack         (dev_ddr3_ref_ack),
   .app_zq_ack          (dev_ddr3_zq_ack),
   .ui_clk              (clk_ddr3_ui),
   .ui_clk_sync_rst     (ui_clk_sync_rst),
   .init_calib_complete (init_calib_complete),
   .device_temp         (device_temp),
   .sys_rst             (nrst)

clk_wiz_0 i_clk_wiz_0
   .reset             (~nrst),
   .clk_in1           (clk),
   .clk_out1          (sysclk),
   .clk_out2          (sysclk_2x),
   .locked            (locked)

  Alchitry a dying project?
Posted by: wdautrem - 04-19-2021, 06:35 PM - Forum: General Questions - Replies (1)

I'm looking to get into FPGA development and was interested in the Alchitry dev board.  Unfortunately, it looks like this product is running out of steam.  Nearly all hardware is out of stock or backordered.  No blog posts for years.  Only a hand full of forum posts this year.  No new element boards being released (HDMI board).  Am I seeing this correctly, or is there another reason for the lack of activity?

  Using Alchitry Labs with Au+
Posted by: howdyrichard - 04-18-2021, 01:11 PM - Forum: General Questions - Replies (1)

Alchitry Labs with Au+, does it work together???

  Compatible boards
Posted by: tagsense - 04-09-2021, 03:19 AM - Forum: General Questions - Replies (1)


I see that none of the development boards - Alchitry CU/AU and Mojo - are available for sale.
Are there other compatible boards one can use for learning? kindly let me know. thank you!

the reason i am asking is I just got the FPGA book (Learning FPGAs: Digital Design for Beginners with Mojo and Lucid HDL).
the book uses Mojo as the FPGA development board.