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  Core naming bug - Alchitry Labs V1.16
Posted by: IvanLentil - 03-29-2020, 02:10 PM - Forum: Tips and Tricks - No Replies

Hi all,

this bug applies in Mojo projects with Xilinx ISE. I haven't checked if it affects with Vivado.

If you use Coregen to build a core, Alchitry Labs uses the default name for the core even if you use a different name when generating it. This can be a problem if you use more than one variant of the same basic core - for example if you use more than one configuration of block ram.

A simple workaround is to exit Alchitry Labs and manually edit the project file to change the core details.

HTH


  Getting started with Alchitry Cu using Yosys, Arachne-pnr and Icepack
Posted by: Zoromoth - 03-26-2020, 07:58 AM - Forum: Tips and Tricks - No Replies

I have made a detailed video explaining the setup and design with Yosys. Link below:

https://www.youtube.com/watch?v=y_jhHcC6...e=youtu.be


  Getting started with Alchitry Cu using Yosys, Arachne-pnr and Icepack
Posted by: Zoromoth - 03-26-2020, 07:00 AM - Forum: Show and Tell - No Replies

I have made a detailed video out lining the setup and design of Alchitry Cu FPGA board. Please do see and rate the video:

https://www.youtube.com/watch?v=y_jhHcC6...e=youtu.be


  Re-flashing a Mojo V3 board
Posted by: Major Havoc - 03-16-2020, 11:17 PM - Forum: General Questions - Replies (6)

Through my own stupidity (connecting more than one board at a time to the computer) I have clobbered the flash loader on my older Mojo v3 dev board, along with the default examples added to that original flash. 

Maybe my search skills are lacking, but I cannot find either the original flash file, or instructions on how to flash a board that is not responding to USB. I am guessing I am going to have to add pins to the JTag and connect and refresh that way? 

Any help would be greatly appreciated. 

-MH


  Alchitry Labs installation corrupt
Posted by: sambuls - 03-12-2020, 07:26 PM - Forum: General Questions - Replies (2)

During the installation of Alchitry Labs or Loader, I receive the following message:

---
The cabinet file 'disk1' required for this installation is corrupt and cannot be used.
This could indicate a network error, an error reading from the CD-ROM, or a problem with this package
---


Re-downloading does not solve the problem


  lucid always block with timing parameters
Posted by: sambuls - 03-09-2020, 03:11 AM - Forum: General Questions - Replies (1)

I created a new clock using the 'vivado IP catalog - clocking wizard'.
Can I use this new clock to run an always block in Lucid?

I could not find any solutions in the 'lucid reference PDF'...

regards


  xbewbie question - setting up icestorm and alchitry labs
Posted by: Prof_Stick - 03-06-2020, 12:37 AM - Forum: General Questions - Replies (1)

After searching the alchitry site and this forum, I cant find a tutorial for setting up alchitry labs with icestorm. Is it just a matter of following the installation instructions on the icestorm homepage and then installing aclhitry labs after icestorm is set up?


  I/O Magic on Au and VHDL
Posted by: Ekkehard - 02-23-2020, 11:18 PM - Forum: General Questions - Replies (2)

I just got a brand new shiny Au two days ago, along with an IO element and a breadboard shield, and I was going through the first couple of Tutorial examples over the weekend, which worked all fine.  But I am afraid, I don't quite understand them, or more precisely, the stuff that goes on behind the scenes.  To begin with, I have no experience or knowledge in Verilog at all, and even less in Lucid - I do know some VHDL though.  

Here is what I don't understand: Who sits on top of the au_top model in Verilog and knows where to route the clk and the rst_n signals, as well as the led vector and the usb_rc and usb_tx signals to?  There must be some correspondence to the physical signals on the board - where is that defined?  And how would I define those if I were to try to convert the tutorials to VHDL, which I would very much like to do to gain some familiarity back? Huh  Where can I find out about these things to read up on?


  XDC Files for Alchitry Au on Vivado
Posted by: tertiary - 02-21-2020, 04:45 AM - Forum: Tips and Tricks - Replies (3)

Just finished making a set of constraint files for using the AU on vivado since I could not find any for the life of me.
One file is for the bare Au (and breakout board Bu). The other file is for the Io shield. It works hand-in-hand with the Au xdc (Ie it does not have the clock or reset button defined in it.)

One thing to note is that the DDR3 definitions are untested and 90% sure they are incorrect. I have been working on these files for hours now and am too tired to look at what their IOSTANDARD values should be in the datasheets. The port locations and the labels are correct however. One day I'll update it to the correct IOSTANDARD values but that day is not today....

The IO shield has all of its inputs pulled down to ground via the fpga's internal pulldowns.



Attached Files
.zip   AlchitryAuIO.zip (Size: 2.57 KB / Downloads: 6)

  Can someone clean up the SPAM?
Posted by: prebys - 02-19-2020, 07:14 PM - Forum: General Questions - Replies (5)

This forum is filling with spam postings, and no one seems to be deleting/blocking them.

Can someone step up?  It's getting unusable.