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Alchitry Hd, Mo, Ft
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Au .bin file loads but ca...
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Lucid V2
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Au can't work
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Can't get the Cu to work....
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  iceprog - Can't find iCE FTDI USB device with Alchitry CU
Posted by: Lopfi - 03-03-2022, 09:13 PM - Forum: General Questions - No Replies

I'm trying to upload my build code to my alchitry-CU FPGA board threw apio using iceprog on windows.

Code:
apio upload

which then executes
Code:
iceprog -d i:0x0403:0x6010:0 hardware.bin

And the output is
Code:
init..
Can't find iCE FTDI USB device (device string i:0x0403:0x6010:0).
ABORT.
scons: *** [upload] Error 2

I have installed the libusbk driver and also tested uploading with the same cable on another pc with the standard drivers and the provided IDE Alchitry Labs in combination with iceCube2 but I really wanted to use the open source alternative instead.


  Moving data into a case statement
Posted by: howdyrichard - 02-22-2022, 12:33 AM - Forum: General Questions - Replies (3)

I have tried and think proved that rx.data cannot cross the case (state.q) boundary.  I can use led = rx.data; before the case statement and the appropriate bits light up.  If I put the same led = rx.data after the case statement, it will not light any lights.

So,

led = rx.data;     /lights appropriate bits

case(state.q) {
  mig.mem_in.en = 1;
  mig.mem_in.cmd = 0;
  mig.mem_in.wr_data = rx.data;
  led = rx.data;                                  //does nothing!

Please explain.  I have spent over a week trying this and that and the only conclusion is there is a problem with Lucid.  If it's a bug, please let me know so I stop spinning my wheels.

Thank you,
howdyrichard


  Passing variables into case statements
Posted by: howdyrichard - 02-20-2022, 04:47 PM - Forum: General Questions - No Replies

I thought I found an answer - wrong.  I tried making a var testbyte and then tying it to rx.data, but that did not work either.  How do I get a byte from rx_uart into a case(state.q) in au_top_plus.luc?  It's the case structure from DDR3 tutorial.

error produced in Alchitry Labs:
Bin file (C:\Users\howdy\Documents\Alchitry\Xilinx\DDR_Test\work\vivado\DDR_Test\DDR_Test.runs\impl_1\au_plus_top_0.bin) could not be found! The build probably failed.

This is a standard error when something is wrong, and "No errors detected" when checking.

This is the error in Vivado:
[Synth 8-1749] cannot have packed dimensions of type integer ["C:/Users/howdy/Documents/Alchitry/Xilinx/DDR_Test/work/vivado/DDR_Test/DDR_Test.srcs/sources_1/imports/verilog/au_plus_top_0.v":163]

This is what I tried:
var testbyte[8];

always {
/* Clock Wizard Connections */
clk_wiz.clk_in1 = clk; // 100MHz in
clk_wiz.reset = !rst_n; // reset signal

rx.rx = usb_rx; // connect rx input
usb_tx = tx.tx; // connect tx output

rx1.rx = dcs_rx;
// dcs_tx = tx1.tx;


then near the case:

testbyte = rx1.data; //rx1.data is from a second uart, the original rx.data is still used as USB_RX

case (state.q) {
state.WRITE_DATA:
mig.mem_in.wr_en = 1;
mig.mem_in.wr_data = testbyte; //trying to use this var to transfer received byte from uart_rx1. Using rx1.data here does nothing but I do not get any errors.
if (mig.mem_out.wr_rdy)
state.d = state.WRITE_CMD;

If I do not specify size of var testbyte[8]; and just say var testbyte; I get this warning from Lucid:


Line 78, Column 15 : The signal "rx1.data" is wider than "testbyte" and the most significant bits will be dropped


  Cloning a project
Posted by: howdyrichard - 02-20-2022, 03:38 PM - Forum: General Questions - Replies (2)

I've been noticing that when I clone a project, rename it and save it in a completely different directory and use this 'new' cloned file, the old source file also gets updated with my new experiments!  Why?


Exclamation Lucid V2
Posted by: alchitry - 02-02-2022, 11:24 PM - Forum: General Questions - Replies (10)

I'm currently working the new parser for Lucid V2. This will be a major update to the Lucid language and will bring many breaking changes.

Currently, these are the changes I'm working on.

  • Optional semicolons. Following the trend of many modern languages, new lines can be used in place of semicolons.
  • Removal the 'var' type. This type never really made much use sense to me. It is functionally equivalent to 'sig' that is 32 bits wide.
  • Replace the 'for' loop with a 'repeat' statement. This will likely have the syntax like "repeat(5: sig) { }" where "sig" would be assigned 0,1,2,3,4 depending on the iteration. For statements are kind of a weird thing to have in hardware since they must have a fixed number of iterations. The "C" style loop used currently and by Verilog is a bit cumbersome and can easily be written to not be a fixed number of iterations.
I'd love some feedback on these changes and any other potential changes you'd like to see make it into this update.

The rest of this post is the nitty gritty of the update.

The original Lucid parser has had feature after feature tacked on to where it is a bit of a mess today. Originally, it only attempted to figure out the width of signals. Then I added stuff that would parse constant expressions so custom functions could be added. Now I want a general interpreter that could be used to build a simulator. This was the motivation behind the full overhaul.

The original parser is broken into a handful of modules here https://github.com/alchitry/Alchitry-Lab...ools/lucid

The main parent is the LucidExtractor. This deals with all the declarations of stuff like modules, dffs, fsms, etc.
The BitWidthChecker attempts to figure out how wide each signal is. It is responsible for giving errors for situations like when you try to assign a struct to an array.
The ConstExprParser was original used to parse constant expressions for functions but has slowly outgrown that role to general expression parsing.
The BoundsParser parses array bounds (like [5:1] or [0+:3])
The ConstParser builds a list of constants declared
The ParamsParser builds a list of parameters declared

There are also a handful of other helper parsers like the LucidGlobalExtractor that parses globals in an initial pass of all the files.

These are all weirdly interdependent which is one of the goals to fix for the new parse.

Currently, the V2 parser handles expressions. I now need to add the rest (variable declarations, various block parsing, global statements, etc)

Its code can be found here https://github.com/alchitry/Alchitry-Lab...rs/lucidv2
The ExprParser is responsible for assigning a Value to every expression. This combines the functionality of the BitWidthChecker and ConstExprParser as these were often redundant. The Value type has an associated width to it and can be an UndefinedValue that still has a width which covers the cases that the BitWidthChecker used to deal with when ConstExprParser couldn't figure out a value.

I also plan to roll some of the small parsers into ExprParser such as BoundsParser (which I added today). Having multiple parsers that are interdependent makes using them difficult.


Information CORE Generator fails to generate core
Posted by: Ferdinand Postema - 01-26-2022, 12:12 AM - Forum: Tips and Tricks - No Replies

Hello,

I'm still using the Mojo-board and installed Xilinx ISE 14.7 on Ubuntu 20.04 (64 bits).
That was running fine until I wanted to generate an IP-core.
The core generator failed every time.
After a long search I finally found the solution on the following web-site: https://wiki.archlinux.org/title/Xilinx_ISE_WebPACK
I had to replace the java-runtime with the java6 runtime as described at the end of the web-site under 'CORE Generator fails to generate core', solution #2.
To be sure I also applied solution #1.

Have a nice day!

Ferdinand Postema


Exclamation Dead LED in display :(
Posted by: TheSwedishLord - 01-25-2022, 04:07 PM - Forum: General Questions - Replies (4)

I contacted my shop about this but what I can find online this is really common problem...
If they refuse to replace it, what do I do?



Attached Files
.jpg   Broken LED.jpg (Size: 431.8 KB / Downloads: 9)

  Shields for the SparkFun DEV-17514 Alchitry Au+ Development Board
Posted by: TheSwedishLord - 01-24-2022, 08:24 PM - Forum: General Questions - Replies (1)

Since I'm new I was thinking of buying some premade shields for my board so I can concentrate on learning instead of building and soldering.

I can really only find 3 shields that is suitable for the Au+, are there more shields in the near future?

There is a Qwiic connector on the board, is there any examples of how to use that?

At the moment I have these

  • SparkFun DEV-17514 Alchitry Au+ Development Board
  • SparkFun DEV-16524 Alchitry Br Prototype Element Board
  • SparkFun Alchitry Io Element Board
  • Alchitry Ft Element Board (soon, ordered but not here yet)
  • A bunch of other electronics, sensors etc that is leftovers from another project, about 20kg Wink
Any nice tutorial for using the Qwiic-port? Bought this breakout SparkFun Atmospheric Sensor Breakout - BME280 (Qwiic) just to lab with the port.
But most important, shields so I can have premade stuff to learn with so any suggestions are welcome.


  Not really aimed at FPGA but…
Posted by: TheSwedishLord - 01-24-2022, 01:42 PM - Forum: General Questions - Replies (2)

I’m a gyrocopter pilot, a hybrid between a ”normal” airplane and a helicopter.
We send radio on the AM band and can trigger the landning lights by sending a carrier signal for 30 seconds.
What I would like to do is to listen for a specific pattern in the signal, pretty much like morse code. So if I push the send button like T-T-T-P-T-T-T-P-T-T-T where T = trigger send and P = pause.
Looks like a good thing to use the FPGA for, I need to constantly monitor the radio with as low latency as possible.

But where do I start, what externa components do I need and what area of defining modules should I look extra at to make this a real winner project?


  JTAG and QSPI Flash on Alchitry Au
Posted by: Wevel - 01-21-2022, 10:32 PM - Forum: General Questions - Replies (2)

Hi,

I'm working on a soft-core CPU design on the Alchitry Au. Ideally, I would like to use the JTAG interface from the FTDI chip to debug and program my cpu with GDB. It looks like I can make use of the BSCANE2 primitive referenced on page 175 of the 7 series FPGA user guide. However, the only example I've found of this primitive being used with the Alchitry Au is in the au-bridge git project, which seems to be undocumented. I want to check making use of this doesn't interfere with how the Alchitry loader writes the bitstream.

Additionally, it would also be nice to have some non-volatile memory to store the CPU's program in. From looking at the schematic, it looks like the on board QSPI flash is used to store the bitstream to initialise the FPGA. But the au-bridge project seems to allow programming this flash, so I would like to know if any of this can be used for user data, or if I would need my own flash chip for this.

Thanks for the help,
Charlie