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Error when Debugging with...
Forum: General Questions
Last Post: Jay8ee
Yesterday, 04:05 PM
» Replies: 2
» Views: 47
Alchitry Au+ new board
Forum: General Questions
Last Post: alchitry
Yesterday, 03:10 PM
» Replies: 1
» Views: 76
Some confusion about Au D...
Forum: General Questions
Last Post: alchitry
Yesterday, 03:07 PM
» Replies: 1
» Views: 36
Register Interface Bug?
Forum: General Questions
Last Post: alchitry
Yesterday, 02:56 PM
» Replies: 1
» Views: 77
Alchitry Labs 1.2.5 - Viv...
Forum: General Questions
Last Post: alchitry
Yesterday, 02:52 PM
» Replies: 1
» Views: 33
How to change Au master c...
Forum: General Questions
Last Post: alchitry
Yesterday, 02:50 PM
» Replies: 1
» Views: 33
Programming Alchitry Au d...
Forum: General Questions
Last Post: Jay8ee
Yesterday, 10:10 AM
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» Views: 41
Wave Capture Example Proj...
Forum: General Questions
Last Post: alchitry
Yesterday, 01:22 AM
» Replies: 1
» Views: 34
Blank Alchitry_AU_Shield ...
Forum: Show and Tell
Last Post: Initerworker
01-01-2021, 03:02 PM
» Replies: 0
» Views: 20
Mojo v3 Java Errors
Forum: General Questions
Last Post: Toast
12-30-2020, 08:09 PM
» Replies: 2
» Views: 166

 
  Error when Debugging with Alchitry Labs 1.2.5
Posted by: Jay8ee - 01-12-2021, 03:50 PM - Forum: General Questions - Replies (2)

Hi.

When I click debug > choose the signals I want in the wave capture, I get the following error:

Code:
java.lang.NullPointerException: Cannot invoke "com.alchitry.labs.parsers.lucid.parser.LucidParser$NameContext.getText()" because the return value of "com.alchitry.labs.parsers.lucid.parser.LucidParser$Output_decContext.name()" is null
    at com.alchitry.labs.parsers.tools.lucid.toVerilog.LucidToVerilog.exitOutput_dec(LucidToVerilog.java:477)
    at com.alchitry.labs.parsers.lucid.parser.LucidParser$Output_decContext.exitRule(LucidParser.java:767)
    at com.alchitry.labs.tools.ParseTreeMultiWalker.exitRule(ParseTreeMultiWalker.java:49)
    at com.alchitry.labs.tools.ParseTreeMultiWalker.walk(ParseTreeMultiWalker.java:31)
    at com.alchitry.labs.tools.ParseTreeMultiWalker.walk(ParseTreeMultiWalker.java:29)
    at com.alchitry.labs.tools.ParseTreeMultiWalker.walk(ParseTreeMultiWalker.java:29)
    at com.alchitry.labs.tools.ParseTreeMultiWalker.walk(ParseTreeMultiWalker.java:29)
    at com.alchitry.labs.tools.ParseTreeMultiWalker.walk(ParseTreeMultiWalker.java:29)
    at com.alchitry.labs.tools.ParserCache.walk(ParserCache.java:127)
    at com.alchitry.labs.parsers.tools.lucid.toVerilog.LucidToVerilog.convert(LucidToVerilog.java:50)
    at com.alchitry.labs.project.builders.ProjectBuilder.getVerilogFile(ProjectBuilder.java:187)
    at com.alchitry.labs.project.builders.ProjectBuilder.getVerilogFiles(ProjectBuilder.java:341)
    at com.alchitry.labs.project.builders.VivadoBuilder.generateProjectFile(VivadoBuilder.java:120)
    at com.alchitry.labs.project.builders.VivadoBuilder.projectBuilder(VivadoBuilder.java:33)
    at com.alchitry.labs.project.builders.ProjectBuilder.build(ProjectBuilder.java:152)
    at com.alchitry.labs.project.Project$build$1.invokeSuspend(Project.kt:1260)
    at kotlin.coroutines.jvm.internal.BaseContinuationImpl.resumeWith(ContinuationImpl.kt:33)
    at kotlinx.coroutines.DispatchedTask.run(DispatchedTask.kt:56)
    at kotlinx.coroutines.scheduling.CoroutineScheduler.runSafely(CoroutineScheduler.kt:571)
    at kotlinx.coroutines.scheduling.CoroutineScheduler$Worker.executeTask(CoroutineScheduler.kt:738)
    at kotlinx.coroutines.scheduling.CoroutineScheduler$Worker.runWorker(CoroutineScheduler.kt:678)
    at kotlinx.coroutines.scheduling.CoroutineScheduler$Worker.run(CoroutineScheduler.kt:665)

Please note that my project builds fine normally. It is basically a blank base AU project (Verilog).

Any ideas? 

Thanks.


  Programming Alchitry Au directly from Vivado
Posted by: tntodorov - 01-12-2021, 06:41 AM - Forum: General Questions - Replies (1)

Is it possible to program the Au directly from Vivado?

If anyone has done it, or has a pointer to more information, it will be very much appreciated! Alternatively, please explain why it is not possible...

Thanks!


  Wave Capture Example Project
Posted by: mdlougheed - 01-10-2021, 09:01 PM - Forum: General Questions - Replies (1)

This 2016 Alchitry blog post mentions a debug wave capture example project, however there is no link to it.
https://alchitry.com/blogs/news/introduc...8b8e&_ss=r

For the Au board, I'm exploring the debug interface and would appreciate learning the proper way to set up wave capture for debug.

Cheers,
MDL


  Alchitry Au+ new board
Posted by: LMN128 - 01-10-2021, 05:05 PM - Forum: General Questions - Replies (1)

Congratulation for new bigger Au board. Is there any change except FPGA chip, please?


  Some confusion about Au DDR3 interface
Posted by: fungineering_101 - 01-07-2021, 07:15 PM - Forum: General Questions - Replies (1)

Hi - I'm trying to work out exactly how this is addressed, and something's wrong with my math.

Starting assumption - it's a 256MB part, and has a 28-bit address field - which is really a 25-bit field since the last 3 are reserved as 0s for ordering.  So there are 2**25 => 33,554,432 distinct addresses.  Which is each address was for an 8-byte block, that multiplies back to 256 MB - but the data in bus is 128-bits / 16 bytes wide?

Do these overlap?  Can I write to address '1' by writing 9 bytes into address '0'?

Alternatively, if it was really a 24-bit address field, with each address being a 16-byte/128-bit block, that would seem like a simpler explanation, if maybe the part interface is shared with a 512MB module and the MSB is unused in the Au's part.


  Register Interface Bug?
Posted by: itsmechuckb - 01-05-2021, 12:55 AM - Forum: General Questions - Replies (1)

I am looking into why, but if anyone else has noticed, please reply. I am using the RegisterInterface.java class to communicate with the reg_interface.luc module. Things are working fine, except when I send 1 integer from the host to the Au using the write method. Multiple integers within the same session work fine. But when one integer is sent, (open port, send one int, close port) I do not get the MSB within the integer transmitted.


  Blank Alchitry_AU_Shield CircuitMaker
Posted by: Initerworker - 01-01-2021, 03:02 PM - Forum: Show and Tell - No Replies

Hi everyone,

I recently had the opportunity to work on my first hardware project for a ham radio SDR Transceiver that I will explain in another thread. I need an ADDA shield, an ADC, and a DAC in Alchitry compatible shield to get my way.

I was a bit disappointed with the lack of information to create our custom shield. So, I decided to dig deep into it and made a straightforward shield design with CircuitMaker and share it with the community.

I warn you that it's my first PCB design, and all your help could be appreciated to improve this blank design.

  • A check on the connector could be helpful :-)
If you want to help me to improve the PCB design, you can ask me to collaborate on this project: If you want to use the design for your purpose, you can fork the project: If you want the connector footprint, you can use this link:
I hope that you will appreciate this opensource contribution,

Best regards,


  Alchitry Labs 1.2.5 - Vivado build log not displaying
Posted by: mdlougheed - 12-31-2020, 01:15 AM - Forum: General Questions - Replies (1)

I'm using AL 1.2.5 with Vivado. During the build, any Vivado log messages are not downing in the AL log pane. I even introduced a deliberate error in the XDC constraints file. Is there a setting in AL, or Vivado that can used to display the build log?

[Image: 103378451-2ec34b80-4a97-11eb-978a-ab449849b9ef.png]


  How to change Au master clock speed through PLL
Posted by: mdlougheed - 12-30-2020, 09:15 PM - Forum: General Questions - Replies (1)

Although it's alluded to, after searching the forum and internet too, I'm unable to find an example of changing the Au boards master clock speed through the on-board PLL.

  • 100MHz on-board clock (can be multiplied internally by the FPGA)
Can this be done using the ACF and XDC constraint files within Alchitry Labs (v1.2.5) or is there further setup within Vivado, in concert with AL that needs doing?  

For the projects I'm contemplating, it would be handy to multiply the clock by 150% and 200%.  For another it's desirable to multiply the clock by 2/3 - that is multiply by 2, then divided by 3.  The Xilinx App Note on Using Constraints hints at how to do this, however is not particularly straightforward, nor is it targeted at AL (which is understandable).

Any HOW-TO from the forum is appreciated.
MDL


  Java Development Kit Error
Posted by: itsmechuckb - 12-25-2020, 11:37 PM - Forum: Tips and Tricks - No Replies

On Windows 10 Pro, AdoptOpenJDK 11 installed, new install of Alchitry Labs. If you get a "This application requires at least Java Development Kit 1.8.0 (64-bit)" dialog when starting Alchitry Labs, it may be because you do not have the JavaSoft registry keys installed or correct for your java runtime environment. When I installed the JDK, the installer had an option to do this. It was turned off by default and I did not elect to turn it on.

This registry hack worked for me:

Code:
Windows Registry Editor Version 5.00

[HKEY_LOCAL_MACHINE\SOFTWARE\JavaSoft]

[HKEY_LOCAL_MACHINE\SOFTWARE\JavaSoft\Java Development Kit]
"CurrentVersion"="1.11"

[HKEY_LOCAL_MACHINE\SOFTWARE\JavaSoft\Java Development Kit\1.11]
"JavaHome"="C:\\Program Files\\AdoptOpenJDK\\jdk-11.0.9.101-hotspot"