Hi everyone.
I have designed a new SDRAM shield for my own mojo board(with exactly the same SDRAM chip).
with two differences in comparison to the original SDRAM shield.

1. I did take it easy and didn't consider high-frequency PCB design stuff(no length matching) I think 100MHz isn't that high, is it?
2. due to some other considerations I've changed some pins:
      sdram_cs        from P115 to P118
      sdram_we       from P111 to P121
      sdram_cas      from P112 to P120
      sdram_ras      from P114 to P119
      sdram_ba<0> from P116 to P117
      sdram_ba<1> from P117 to P116
      sdram_a<0>  from P118 to P115
      sdram_a<1>  from P119 to P114
      sdram_a<2>  from P120 to P112
      sdram_a<3>  from P121 to P111
it means they are two-by-two changed as below:
P115  <> P118
P121  <> P111
P120  <> P112
P114  <> P119
P116  <> P117


mojo SDRAM test example with modified UCF does not work. (It acts as there is no SDRAM-shield on Mojo board)

Do you think what could be the cause of the problem?
Is 100 Mhz considered high such that could cause this problem? (I even reduced the clock but no achievement)

or could changing pins cause this problem?

Thanks

Hello,

I am simply an experimenter and trying to learn more about FPGAs. I came across the Alchistry products and appeared to be a reasonable way to start. I understand I should be use Alcitry Labs to develop and experiment with the AU board. On reading about installation, I discovered I needed to install Vivado from Xilinx as well. I went to Xilinx's website and discovered that I needed to fill in a form pertaining to US Government approval for exports. I have filled such forms many time in the past while employed by various organisations. My purpose for learning about FPGAs is strictly as a personal project. How do I obtain Vivado if I do not want to include an employer's name or company name on the application form? I live in Australia which has always been on friendly terms with the US

Thanks.

Hello there! I' m trying to use the Alchitry Au+, with the Alchitry Ft element board to build a system that could receive data from an external ADC from the Usb 3.0 port of the Ft board.
I' m quite new to the world of the FPGAs, so I' m looking for advice if you have, in particular on how to adapt the Mojo tutorials also for Alchitry Au+, beacuse I saw that most of the tutorials are on the Mojo board. If  you have suggestions about how to interface the Au+ with the ADC, are welcome, or also tips of any tipe.
Thank you!

Hi!
I want to program my Alchitry Au+ directly using Xilinx Platform Cable USB II. I hope that this way I will be able to use live on-chip debugging in Xilinx Vivado.
But it doesn't work for me.   

I'm using Alchitry Br Prototype Element Board, which has pins for TDI, TDO, TCK and TMS. I connect Xilinx Cable to these four pins. Then I connect GND and +3.3V pins. I'm powering the board by a lab power supply using Raw +5V pin.

The Alchtiry Au+ seems to be alive (a configuration stored in flash runs OK). Status led on Xilinx Cable is green.
But Vivado Hardware Manager says that no board is connected.
(I know that the Xilinx Cable works. It operates without problem with this board.) 

What am I doing wrong?

Viktor


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It will not create the Stub file whether I use the above zip or the Au code (same results). I am using Au+. This is the error in Vivado: mig_7series_0_synth_1, Synthesis Out-of-date. Under Chang Log there are 5 errors, netlist.v are and stub.v are two of them. I did fid an article on how to make out of date be ignored but due to upgrades since 2018 I cannot find how to do it.

I saw somewhere that if a Au+ board is used then a stub file is not required.  I cannot get past the Synthesis Out-of-date error.  Anyone know the solution to this?  I am using Vivado 2020.2.

Thank you!

I bought an Alchitry Au about a year ago from SparkFun and finally got around to checking it out this past weekend, however I can't get it to be recognized by the Alchitry Loader. I am running on Ubuntu Linux 20.10 and am not using alchitry labs (am using Vivado/Verilog instead of Alchitry Labs and Lucid).

The board seems to power on just fine and the leds do this wave pattern and an alternating LED pattern when the reset button is pressed down, so I assume its working ok.

I also checked dmesg and it appears that everything is being hooked up just fine there, so I am not really sure what is going on.

I found through the process of elimination that the line

    scale = $pow(10, j);

in the bin_to_dec component caused my build to fail. Of course it is easy enough to replace it with a simple loop and that is what I did to get around the problem.

My best guess is that the problem occurs when alchitry labs converts lucid to verilog.

The Kparser could not open the .edf file.

Also note that I break the build into two steps:

1. use alchitry labs to generate the verilog and whatever else it does
2. run work\build.cmd manually to finish the build

This is due to the previous problem that I had with alchitry labs and is documented in my previous posts.

I might be blind, but I couldn't find an example project for the Element FT anywhere. Does it exist anywhere or I'm completely on my own with it?

Here's a picture of attempting to display all 8s - a bunch of segments aren't displaying, and they're different on the different displays. I'm doing this with IceCube2 and not Alchitry Labs as I'm having the dreaded "cu_top_0_bitmap.bin) could not be found!" error in Alchitry Labs. Not sure if this is relevant.


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I'm not sure what this means, any advice? Also not having pull downs is annoying, if anyone has verilog code to have intermittent pull-downs, please post it.

Hi folks,

I'm a beginner using the Alchitry Au+, currently working through the tutorials to get familiar with Lucid and the board. It works fine, I have no complaints so far.

The only thing that I'm missing is some configurability. I have an older machine with an i-8500 Processor, 6 cores. 
I noticed that in the project.tcl file the number of processors to be used seems to be hard coded to 8, so Vivado falls back to use only 2 cores. Since the build is a lengthy process, I'd like to set it to the correct value of 6 cores. Faster is better 

Is there any way to modify the number of cores in the project.tcl? Is there any way to help Alchitry Labs generate a corrected "project.tcl"?