It will not create the Stub file whether I use the above zip or the Au code (same results). I am using Au+. This is the error in Vivado: mig_7series_0_synth_1, Synthesis Out-of-date. Under Chang Log there are 5 errors, netlist.v are and stub.v are two of them. I did fid an article on how to make out of date be ignored but due to upgrades since 2018 I cannot find how to do it.

I saw somewhere that if a Au+ board is used then a stub file is not required.  I cannot get past the Synthesis Out-of-date error.  Anyone know the solution to this?  I am using Vivado 2020.2.

Thank you!

I bought an Alchitry Au about a year ago from SparkFun and finally got around to checking it out this past weekend, however I can't get it to be recognized by the Alchitry Loader. I am running on Ubuntu Linux 20.10 and am not using alchitry labs (am using Vivado/Verilog instead of Alchitry Labs and Lucid).

The board seems to power on just fine and the leds do this wave pattern and an alternating LED pattern when the reset button is pressed down, so I assume its working ok.

I also checked dmesg and it appears that everything is being hooked up just fine there, so I am not really sure what is going on.

I found through the process of elimination that the line

    scale = $pow(10, j);

in the bin_to_dec component caused my build to fail. Of course it is easy enough to replace it with a simple loop and that is what I did to get around the problem.

My best guess is that the problem occurs when alchitry labs converts lucid to verilog.

The Kparser could not open the .edf file.

Also note that I break the build into two steps:

1. use alchitry labs to generate the verilog and whatever else it does
2. run work\build.cmd manually to finish the build

This is due to the previous problem that I had with alchitry labs and is documented in my previous posts.

I might be blind, but I couldn't find an example project for the Element FT anywhere. Does it exist anywhere or I'm completely on my own with it?

Here's a picture of attempting to display all 8s - a bunch of segments aren't displaying, and they're different on the different displays. I'm doing this with IceCube2 and not Alchitry Labs as I'm having the dreaded "cu_top_0_bitmap.bin) could not be found!" error in Alchitry Labs. Not sure if this is relevant.


  IMG_0384.JPG (Size: 91.93 KB / Downloads: 12)

I'm not sure what this means, any advice? Also not having pull downs is annoying, if anyone has verilog code to have intermittent pull-downs, please post it.

Hi folks,

I'm a beginner using the Alchitry Au+, currently working through the tutorials to get familiar with Lucid and the board. It works fine, I have no complaints so far.

The only thing that I'm missing is some configurability. I have an older machine with an i-8500 Processor, 6 cores. 
I noticed that in the project.tcl file the number of processors to be used seems to be hard coded to 8, so Vivado falls back to use only 2 cores. Since the build is a lengthy process, I'd like to set it to the correct value of 6 cores. Faster is better 

Is there any way to modify the number of cores in the project.tcl? Is there any way to help Alchitry Labs generate a corrected "project.tcl"?

Hello,

I recently bought an Alchitry Au and I am planning to use Alchitry Labs to program it. Unfortunately, for reasons which I really can't understand, I cannot synthesis anything from this IDE. When I push the little hammer button, the IDE says "Starting Vivado..." but then it stays like this forever.

Let me provide more info below :

- I am using Vivado 2020.1 and it works perfectly with the Alchitry Au board,
- My java is updated to the latest version, i.e. 1.8.0_291-b10,
- The Alchitry Labs version is 1.2.6,
- Everything is installed on a regularly updated Windows 10 machine.

Any idea why I am not able to build anything from this IDE? Obviously, I will provide more information, if necessary, to whoever wants to help me.

Thanks!

Tried to build 1st example for a Cu board using Lucid when I got this error:

Bin file (C:\Users\David\Documents\alchitry\CuLEDtoButton\work\alchitry_imp\sbt\outputs\bitmap\cu_top_0_bitmap.bin) could not be found! The build probably failed.

I see in the forum where one fellow seemed to solve the problem but he wasn't kind enough to provide the solution!!!!!

I'm having some problems running the "memory interface generator" in vivado.
I'm trying to configure the DDR3 basic on the schematic and XDC files, however I get an error;

Does Alchitry have the hardware description file for the Au board?  I think it is referred to as an xsa file.