Hi.

When I click debug > choose the signals I want in the wave capture, I get the following error:

Is it possible to program the Au directly from Vivado?

If anyone has done it, or has a pointer to more information, it will be very much appreciated! Alternatively, please explain why it is not possible...

Thanks!

This 2016 Alchitry blog post mentions a debug wave capture example project, however there is no link to it.
https://alchitry.com/blogs/news/introduc...8b8e&_ss=r

For the Au board, I'm exploring the debug interface and would appreciate learning the proper way to set up wave capture for debug.

Cheers,
MDL

Congratulation for new bigger Au board. Is there any change except FPGA chip, please?

Hi - I'm trying to work out exactly how this is addressed, and something's wrong with my math.

Starting assumption - it's a 256MB part, and has a 28-bit address field - which is really a 25-bit field since the last 3 are reserved as 0s for ordering.  So there are 2**25 => 33,554,432 distinct addresses.  Which is each address was for an 8-byte block, that multiplies back to 256 MB - but the data in bus is 128-bits / 16 bytes wide?

Do these overlap?  Can I write to address '1' by writing 9 bytes into address '0'?

Alternatively, if it was really a 24-bit address field, with each address being a 16-byte/128-bit block, that would seem like a simpler explanation, if maybe the part interface is shared with a 512MB module and the MSB is unused in the Au's part.

I am looking into why, but if anyone else has noticed, please reply. I am using the RegisterInterface.java class to communicate with the reg_interface.luc module. Things are working fine, except when I send 1 integer from the host to the Au using the write method. Multiple integers within the same session work fine. But when one integer is sent, (open port, send one int, close port) I do not get the MSB within the integer transmitted.

Hi everyone,

I recently had the opportunity to work on my first hardware project for a ham radio SDR Transceiver that I will explain in another thread. I need an ADDA shield, an ADC, and a DAC in Alchitry compatible shield to get my way.

I was a bit disappointed with the lack of information to create our custom shield. So, I decided to dig deep into it and made a straightforward shield design with CircuitMaker and share it with the community.

I warn you that it's my first PCB design, and all your help could be appreciated to improve this blank design.

• A check on the connector could be helpful :-)
  

• https://workspace.circuitmaker.com/Proje...ryAUShield
  

• https://workspace.circuitmaker.com/Proje...ryAUShield
  

• https://workspace.circuitmaker.com/Compo...352E9FF0C3
  

I'm using AL 1.2.5 with Vivado. During the build, any Vivado log messages are not downing in the AL log pane. I even introduced a deliberate error in the XDC constraints file. Is there a setting in AL, or Vivado that can used to display the build log?

Although it's alluded to, after searching the forum and internet too, I'm unable to find an example of changing the Au boards master clock speed through the on-board PLL.

• 100MHz on-board clock (can be multiplied internally by the FPGA)

On Windows 10 Pro, AdoptOpenJDK 11 installed, new install of Alchitry Labs. If you get a "This application requires at least Java Development Kit 1.8.0 (64-bit)" dialog when starting Alchitry Labs, it may be because you do not have the JavaSoft registry keys installed or correct for your java runtime environment. When I installed the JDK, the installer had an option to do this. It was turned off by default and I did not elect to turn it on.

This registry hack worked for me: